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target/riscv: Use existent 128-bit load/store hooks to emulate whole …
…reg rvv loads/stores. This commit removes the custom tcg gvec nodes used to attempt to emulate the whole register loads and stores and uses instead the tcg_gen_qemu_[ld,st]_i128 and tcg_gen_[st,ld]_i128 functions to load from memory to vector register and viceversa when emulating a whole register vector load or store. Whole register loads and store will always load and store at least 16 bytes but we need to add checks on atomicity for the host and possibly endianness when calculating the memory addresses. If necessary these loads and store can be broken into i64, i32, i16, i8.
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