target/riscv: add endianness check when optimizing small vector loads…

… and stores.

This patch adds a condition on the endianness of the host for the emulation
of vector loads and store to be done with an optimized loop.
We add this because such optimization doesn't work for big endian hosts.

Signed-off-by: Paolo Savini <[email protected]>

target/riscv/vector_helper.c

@@ -393,7 +393,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
         return;
     }
 
-#ifdef CONFIG_USER_ONLY
+#if defined(CONFIG_USER_ONLY) && !HOST_BIG_ENDIAN
     /* For data sizes <= 64 bits and for LMUL=1 with VLEN=128 bits we get a
      * better performance by doing a simple simulation of the load/store
      * without the overhead of prodding the host RAM */