build: io: make oe2 of DDRTristate optional

make oe2 of DDRTristate optional. Signed-off-by: Fin Maaß <[email protected]>
enjoy-digital · Sep 18, 2024 · 37ac79b · 37ac79b
1 parent abc8f9b
commit 37ac79b
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Showing 4 changed files with 6 additions and 5 deletions.
diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py
@@ -252,7 +252,7 @@ def lower(dr):
 
 class EfinixDDRTristateImpl(Module):
     def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk):
-        assert oe1 == oe2
+        assert oe2 is None
         io_name = platform.get_pin_name(io)
         io_pad  = platform.get_pin_location(io)
         io_prop = platform.get_pin_properties(io)

diff --git a/litex/build/io.py b/litex/build/io.py
@@ -184,12 +184,12 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
         _oe = Signal()
         _i  = Signal()
         self.specials += DDROutput(o1, o2, _o, clk)
-        self.specials += DDROutput(oe1, oe2, _oe, clk)
+        self.specials += DDROutput(oe1, oe2, _oe, clk) if oe2 is not None else SDROutput(oe1, _oe, clk)
         self.specials += DDRInput(_i, i1, i2, clk)
         self.specials += Tristate(io, _o, _oe, _i)
 
 class DDRTristate(Special):
-    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=ClockSignal()):
+    def __init__(self, io, o1, o2, oe1, oe2=None, i1=Signal(), i2=Signal(), clk=ClockSignal()):
         Special.__init__(self)
         self.io  = io
         self.o1  = o1

diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
@@ -305,11 +305,12 @@ def lower(dr):
 
 class LatticeNXDDRTristateImpl(Module):
     def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+        assert oe2 is None
         _o  = Signal()
         _oe = Signal()
         _i  = Signal()
         self.specials += DDROutput(o1, o2, _o, clk)
-        self.specials += SDROutput(oe1 | oe2, _oe, clk)
+        self.specials += SDROutput(oe1, _oe, clk)
         self.specials += DDRInput(_i, i1, i2, clk)
         self.specials += Tristate(io, _o, _oe, _i)
         _oe.attr.add("syn_useioff")

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
@@ -164,7 +164,7 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
         _oe_n = Signal()
         _i    = Signal()
         self.specials += DDROutput(o1, o2, _o, clk)
-        self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk)
+        self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk) if oe2 is not None else SDROutput(~oe1, _oe_n, clk)
         self.specials += DDRInput(_i, i1, i2, clk)
         self.specials += Instance("IOBUF",
             io_IO = io,