Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Vexiiriscv update #2102

Merged
merged 3 commits into from
Oct 28, 2024
Merged

Vexiiriscv update #2102

merged 3 commits into from
Oct 28, 2024

Conversation

Dolu1990
Copy link
Collaborator

@Dolu1990 Dolu1990 commented Oct 24, 2024 •
edited
Loading

This PR bring improve the VexiiRiscv core with :

  • Better timings
  • all RV32/64 x RVF RVD legal combination supported
  • VexiiRiscv SoC now support the ethernet rgmii with DMA accesses.

The ethernet RGMII driver can be found here :

@enjoy-digital
Copy link
Owner

Nice, thanks @Dolu1990!

@enjoy-digital enjoy-digital merged commit 23df960 into enjoy-digital:master Oct 28, 2024
1 check failed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@Dolu1990 @enjoy-digital