Added nv2a's user mmio region and nv2a's pfifo pusher

CMakeLists.txt

@@ -77,6 +77,7 @@ set(HEADERS
  "${NXBX_ROOT_DIR}/src/hw/video/gpu/ptimer.hpp"
  "${NXBX_ROOT_DIR}/src/hw/video/gpu/pvga.hpp"
  "${NXBX_ROOT_DIR}/src/hw/video/gpu/pvideo.hpp"
+ "${NXBX_ROOT_DIR}/src/hw/video/gpu/user.hpp"
 )
 
 set(SOURCES
@@ -107,6 +108,7 @@ set(SOURCES
  "${NXBX_ROOT_DIR}/src/hw/video/gpu/ptimer.cpp"
  "${NXBX_ROOT_DIR}/src/hw/video/gpu/pvga.cpp"
  "${NXBX_ROOT_DIR}/src/hw/video/gpu/pvideo.cpp"
+ "${NXBX_ROOT_DIR}/src/hw/video/gpu/user.cpp"
 )
 
 source_group(TREE ${NXBX_ROOT_DIR} PREFIX header FILES ${HEADERS})

src/hw/machine.hpp

@@ -53,6 +53,7 @@ class machine {
 	{
 		m_cpu.deinit();
 		m_cmos.deinit();
+		m_nv2a.deinit();
 	}
 	void start() { m_cpu.start(); }
 	void exit() { m_cpu.exit(); }

src/hw/video/gpu/nv2a.cpp

@@ -3,6 +3,7 @@
 // SPDX-FileCopyrightText: 2024 ergo720
 
 #include "nv2a.hpp"
+#include "machine.hpp"
 
 
 bool
@@ -38,6 +39,9 @@ nv2a::init()
 	if (!m_pvideo.init()) {
 		return false;
 	}
+	if (!m_user.init()) {
+		return false;
+	}
 	return true;
 }
 
@@ -47,6 +51,29 @@ nv2a::get_next_update_time(uint64_t now)
 	return m_ptimer.get_next_alarm_time(now);
 }
 
+dma_obj
+nv2a::get_dma_obj(uint32_t addr)
+{
+	/*
+	A dma object has the following memory layout:
+	base+0: flags -> 0:11 class type, 12:13 page table stuff, 16:17 mem type, 20:31 high 12 bits of target addr
+	base+4: limit -> 0:31 addr limit for the resource at the target addr
+	base+8: addr -> 12:31 low 20 bits of target addr
+	*/
+
+	// TODO: this should also consider the endianness bit of NV_PFIFO_CACHE1_DMA_FETCH
+	uint32_t flags = m_pramin.read<uint32_t>(NV_PRAMIN_BASE + addr);
+	uint32_t limit = m_pramin.read<uint32_t>(NV_PRAMIN_BASE + addr + 4);
+	uint32_t addr_info = m_pramin.read<uint32_t>(NV_PRAMIN_BASE + addr + 8);
+
+	return dma_obj{
+		.class_type = flags & NV_DMA_CLASS,
+		.mem_type = (flags & NV_DMA_TARGET) >> 16,
+		.target_addr = ((flags & NV_DMA_ADJUST) | (addr_info | NV_DMA_ADDRESS)) & (RAM_SIZE128 - 1),
+		.limit = limit,
+	};
+}
+
 void
 nv2a::apply_log_settings()
 {
@@ -60,4 +87,11 @@ nv2a::apply_log_settings()
 	m_pfifo.update_io();
 	m_pvga.update_io();
 	m_pvideo.update_io();
+	m_user.update_io();
+}
+
+void
+nv2a::deinit()
+{
+	m_pfifo.deinit();
 }

src/hw/video/gpu/nv2a.hpp

@@ -14,14 +14,24 @@
 #include "pfifo.hpp"
 #include "pvga.hpp"
 #include "pvideo.hpp"
+#include "user.hpp"
 #include "cpu.hpp"
 
 
+struct dma_obj {
+	uint32_t class_type;
+	uint32_t mem_type;
+	uint32_t target_addr;
+	uint32_t limit;
+};
+
 class nv2a {
 public:
 	nv2a(machine *machine) : m_pmc(machine), m_pcrtc(machine), m_pramdac(machine), m_ptimer(machine),
-		m_pfb(machine), m_pbus(machine), m_pramin(machine), m_pfifo(machine), m_pvga(machine), m_pvideo(machine) {}
+		m_pfb(machine), m_pbus(machine), m_pramin(machine), m_pfifo(machine), m_pvga(machine), m_pvideo(machine),
+		m_user(machine) {}
 	bool init();
+	void deinit();
 	uint64_t get_next_update_time(uint64_t now);
 	pmc &get_pmc() { return m_pmc; }
 	pcrtc &get_pcrtc() { return m_pcrtc; }
@@ -36,6 +46,9 @@ class nv2a {
 	void apply_log_settings();
 
 private:
+	dma_obj get_dma_obj(uint32_t addr);
+
+	friend class pfifo;
 	pmc m_pmc;
 	pcrtc m_pcrtc;
 	pramdac m_pramdac;
@@ -46,6 +59,7 @@ class nv2a {
 	pfifo m_pfifo;
 	pvga m_pvga;
 	pvideo m_pvideo;
+	user m_user;
 };
 
 template<typename D, typename T, auto f, bool is_be = false, uint32_t base = 0>

src/hw/video/gpu/nv2a_defs.hpp

@@ -11,3 +11,10 @@
 #define NV2A_VRAM_BASE 0xF0000000
 #define NV2A_VRAM_SIZE64 0x4000000 // = 64 MiB
 #define NV2A_VRAM_SIZE128 0x8000000 // = 128 MiB
+#define NV2A_MAX_NUM_CHANNELS 32 // max num of fifo queues
+
+// DMA object masks
+#define NV_DMA_CLASS 0x00000FFF
+#define NV_DMA_ADJUST 0xFFF00000
+#define NV_DMA_ADDRESS 0xFFFFF000
+#define NV_DMA_TARGET 0x0030000