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RISCV: remove the direct-vectoring & interrupt-preemption features and enable them by default #3859

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RISCV: remove the direct-vectoring & interrupt-preemption features and enable them by default

RISCV: remove the direct-vectoring & interrupt-preemption features and enable them by default #3859

Triggered via pull request March 19, 2024 00:26
@MabezDevMabezDev
synchronize #1310
MabezDev:direct-vectoring-by-default
Status Failure
Total duration 6m 55s
Artifacts –

ci.yml

on: pull_request
esp-riscv-rt
46s
esp-riscv-rt
msrv-riscv
2m 2s
msrv-riscv
msrv-xtensa
3m 49s
msrv-xtensa
clippy-riscv
2m 1s
clippy-riscv
clippy-xtensa
3m 4s
clippy-xtensa
rustfmt
20s
rustfmt
Matrix: esp-hal
Matrix: esp-lp-hal
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4 errors
esp-hal (esp32c2)
Process completed with exit code 1.
esp-hal (esp32c3)
Process completed with exit code 1.
esp-hal (esp32h2)
Process completed with exit code 1.
esp-hal (esp32c6)
Process completed with exit code 1.