Clean up (#920)

esp-rs · Nov 10, 2023 · 07ed22d · 07ed22d
1 parent 6b0a16f
commit 07ed22d
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Showing 13 changed files with 87 additions and 80 deletions.
diff --git a/esp-hal-common/src/aes/mod.rs b/esp-hal-common/src/aes/mod.rs
@@ -1,19 +1,25 @@
 //! # Advanced Encryption Standard (AES) support.
 //!
 //! ## Overview
+//!
 //! The AES module provides an interface to interact with the AES peripheral,
 //! provides encryption and decryption capabilities for ESP chips using the AES
 //! algorithm. We currently support the following AES encryption modes:
+//!
 //! * AES-128
 //! * AES-192
 //! * AES-256
 //!
 //! ## Example
+//!
 //! ### Initialization
+//!
 //! ```no_run
 //! let mut aes = Aes::new(peripherals.AES);
 //! ```
+//!
 //! ### Creating key and block Buffer
+//!
 //! ```no_run
 //! let keytext = "SUp4SeCp@sSw0rd".as_bytes();
 //! let plaintext = "message".as_bytes();
@@ -28,6 +34,7 @@
 //! ```
 //!
 //! ### Encrypting and Decrypting (using hardware)
+//!
 //! ```no_run
 //! let mut block = block_buf.clone();
 //! aes.process(&mut block, Mode::Encryption128, &keybuf);
@@ -38,6 +45,7 @@
 //! ```
 //!
 //! ### Encrypting and Decrypting (using software)
+//!
 //! ```no_run
 //! let key = GenericArray::from(keybuf);
 //!
@@ -52,13 +60,19 @@
 //! ```
 //!
 //! ### Implementation State
+//!
 //! * DMA mode is currently not supported on ESP32 and ESP32S2 ⚠️
+//!
 //! ## DMA-AES Mode
+//!
 //! Supports 6 block cipher modes including `ECB/CBC/OFB/CTR/CFB8/CFB128`.
+//!
 //! * Initialization vector (IV) is currently not supported ⚠️
 //!
 //! ## Example
-//! ### Initializaton
+//!
+//! ### Initialization
+//!
 //! ```no_run
 //! let dma = Gdma::new(peripherals.DMA);
 //! let dma_channel = dma.channel0;
@@ -75,6 +89,7 @@
 //! ```
 //!
 //! ### Operation
+//!
 //! ```no_run
 //! let transfer = aes
 //!     .process(
@@ -312,6 +327,8 @@ pub mod dma {
             self,
         ) -> Result<(RXBUF, TXBUF, AesDma<'d, C>), (DmaError, RXBUF, TXBUF, AesDma<'d, C>)>
         {
+            // Waiting for the DMA transfer is not enough. We need to wait for the
+            // peripheral to finish flushing its buffers, too.
             while self.aes_dma.aes.aes.state.read().state().bits() != 2 // DMA status DONE == 2
                 && !self.aes_dma.channel.tx.is_done()
             {
@@ -320,6 +337,8 @@ pub mod dma {
 
             self.aes_dma.finish_transform();
 
+            let err = self.aes_dma.channel.rx.has_error() || self.aes_dma.channel.tx.has_error();
+
             // `DmaTransferRxTx` needs to have a `Drop` implementation, because we accept
             // managed buffers that can free their memory on drop. Because of that
             // we can't move out of the `DmaTransferRxTx`'s fields, so we use `ptr::read`
@@ -331,8 +350,6 @@ pub mod dma {
                 let rbuffer = core::ptr::read(&self.rbuffer);
                 let tbuffer = core::ptr::read(&self.tbuffer);
                 let payload = core::ptr::read(&self.aes_dma);
-                let err = (&self).aes_dma.channel.rx.has_error()
-                    || (&self).aes_dma.channel.tx.has_error();
                 mem::forget(self);
                 if err {
                     Err((DmaError::DescriptorError, rbuffer, tbuffer, payload))

diff --git a/esp-hal-common/src/i2s.rs b/esp-hal-common/src/i2s.rs
@@ -393,7 +393,10 @@ where
     fn wait(
         self,
     ) -> Result<(BUFFER, I2sTx<'d, T, P, CH>), (DmaError, BUFFER, I2sTx<'d, T, P, CH>)> {
-        self.i2s_tx.wait_tx_dma_done().ok(); // waiting for the DMA transfer is not enough
+        // Waiting for the DMA transfer is not enough. We need to wait for the
+        // peripheral to finish flushing its buffers, too.
+        self.i2s_tx.wait_tx_dma_done().ok();
+        let err = self.i2s_tx.tx_channel.has_error();
 
         // `DmaTransfer` needs to have a `Drop` implementation, because we accept
         // managed buffers that can free their memory on drop. Because of that
@@ -405,7 +408,6 @@ where
         unsafe {
             let buffer = core::ptr::read(&self.buffer);
             let payload = core::ptr::read(&self.i2s_tx);
-            let err = (&self).i2s_tx.tx_channel.has_error();
             core::mem::forget(self);
             if err {
                 Err((DmaError::DescriptorError, buffer, payload))
@@ -496,9 +498,11 @@ where
         dst: &mut [u8],
     ) -> Result<(BUFFER, I2sRx<'d, T, P, CH>, usize), (DmaError, BUFFER, I2sRx<'d, T, P, CH>, usize)>
     {
-        self.i2s_rx.wait_rx_dma_done().ok(); // waiting for the DMA transfer is not enough
-
+        // Waiting for the DMA transfer is not enough. We need to wait for the
+        // peripheral to finish flushing its buffers, too.
+        self.i2s_rx.wait_rx_dma_done().ok();
         let len = self.i2s_rx.rx_channel.drain_buffer(dst).unwrap();
+        let err = self.i2s_rx.rx_channel.has_error();
 
         // `DmaTransfer` needs to have a `Drop` implementation, because we accept
         // managed buffers that can free their memory on drop. Because of that
@@ -510,7 +514,6 @@ where
         unsafe {
             let buffer = core::ptr::read(&self.buffer);
             let payload = core::ptr::read(&self.i2s_rx);
-            let err = (&self).i2s_rx.rx_channel.has_error();
             core::mem::forget(self);
             if err {
                 Err((DmaError::DescriptorError, buffer, payload, len))
@@ -533,7 +536,10 @@ where
     fn wait(
         self,
     ) -> Result<(BUFFER, I2sRx<'d, T, P, CH>), (DmaError, BUFFER, I2sRx<'d, T, P, CH>)> {
-        self.i2s_rx.wait_rx_dma_done().ok(); // waiting for the DMA transfer is not enough
+        // Waiting for the DMA transfer is not enough. We need to wait for the
+        // peripheral to finish flushing its buffers, too.
+        self.i2s_rx.wait_rx_dma_done().ok();
+        let err = self.i2s_rx.rx_channel.has_error();
 
         // `DmaTransfer` needs to have a `Drop` implementation, because we accept
         // managed buffers that can free their memory on drop. Because of that
@@ -545,7 +551,6 @@ where
         unsafe {
             let buffer = core::ptr::read(&self.buffer);
             let payload = core::ptr::read(&self.i2s_rx);
-            let err = (&self).i2s_rx.rx_channel.has_error();
             core::mem::forget(self);
             if err {
                 Err((DmaError::DescriptorError, buffer, payload))

diff --git a/esp-hal-common/src/parl_io.rs b/esp-hal-common/src/parl_io.rs
@@ -1247,14 +1247,14 @@ where
     pub fn wait(
         self,
     ) -> Result<(BUFFER, ParlIoTx<'d, C, P, CP>), (DmaError, BUFFER, ParlIoTx<'d, C, P, CP>)> {
-        loop {
-            if Instance::is_tx_eof() {
-                break;
-            }
-        }
+        // Waiting for the DMA transfer is not enough. We need to wait for the
+        // peripheral to finish flushing its buffers, too.
+        while !Instance::is_tx_eof() {}
 
         Instance::set_tx_start(false);
 
+        let err = self.instance.tx_channel.has_error();
+
         // `DmaTransfer` needs to have a `Drop` implementation, because we accept
         // managed buffers that can free their memory on drop. Because of that
         // we can't move out of the `DmaTransfer`'s fields, so we use `ptr::read`
@@ -1265,7 +1265,6 @@ where
         unsafe {
             let buffer = core::ptr::read(&self.buffer);
             let payload = core::ptr::read(&self.instance);
-            let err = (&self).instance.tx_channel.has_error();
             mem::forget(self);
             if err {
                 Err((DmaError::DescriptorError, buffer, payload))