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update adc pac (#1506)
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@burrbull
burrbull authored Apr 29, 2024
1 parent 840c395 commit 157ac17
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Showing 3 changed files with 30 additions and 58 deletions.
14 changes: 7 additions & 7 deletions esp-hal/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -52,13 +52,13 @@ xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true }
esp32 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.8.0", path = "../esp-riscv-rt" }
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50 changes: 20 additions & 30 deletions esp-hal/src/analog/adc/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -181,12 +181,9 @@ impl RegisterAccess for crate::peripherals::ADC1 {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.onetime_sample().modify(|_, w| unsafe {
w.saradc1_onetime_sample()
.set_bit()
.saradc_onetime_channel()
.bits(channel)
.saradc_onetime_atten()
.bits(attenuation)
w.saradc1_onetime_sample().set_bit();
w.onetime_channel().bits(channel);
w.onetime_atten().bits(attenuation)
});
}

Expand All @@ -195,19 +192,19 @@ impl RegisterAccess for crate::peripherals::ADC1 {

sar_adc
.onetime_sample()
.modify(|_, w| w.saradc_onetime_start().set_bit());
.modify(|_, w| w.onetime_start().set_bit());
}

fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.int_raw().read().apb_saradc1_done().bit()
sar_adc.int_raw().read().adc1_done().bit()
}

fn read_data() -> u16 {
let sar_adc = unsafe { &*APB_SARADC::PTR };

(sar_adc.sar1data_status().read().apb_saradc1_data().bits() as u16) & 0xfff
(sar_adc.sar1data_status().read().saradc1_data().bits() as u16) & 0xfff
}

fn reset() {
Expand All @@ -216,12 +213,12 @@ impl RegisterAccess for crate::peripherals::ADC1 {
// Clear ADC1 sampling done interrupt bit
sar_adc
.int_clr()
.write(|w| w.apb_saradc1_done().clear_bit_by_one());
.write(|w| w.adc1_done().clear_bit_by_one());

// Disable ADC sampling
sar_adc
.onetime_sample()
.modify(|_, w| w.saradc_onetime_start().clear_bit());
.modify(|_, w| w.onetime_start().clear_bit());
}

fn set_init_code(data: u16) {
Expand Down Expand Up @@ -292,12 +289,9 @@ impl RegisterAccess for crate::peripherals::ADC2 {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.onetime_sample().modify(|_, w| unsafe {
w.saradc2_onetime_sample()
.set_bit()
.saradc_onetime_channel()
.bits(channel)
.saradc_onetime_atten()
.bits(attenuation)
w.saradc2_onetime_sample().set_bit();
w.onetime_channel().bits(channel);
w.onetime_atten().bits(attenuation)
});
}

Expand All @@ -306,31 +300,31 @@ impl RegisterAccess for crate::peripherals::ADC2 {

sar_adc
.onetime_sample()
.modify(|_, w| w.saradc_onetime_start().set_bit());
.modify(|_, w| w.onetime_start().set_bit());
}

fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.int_raw().read().apb_saradc2_done().bit()
sar_adc.int_raw().read().adc2_done().bit()
}

fn read_data() -> u16 {
let sar_adc = unsafe { &*APB_SARADC::PTR };

(sar_adc.sar2data_status().read().apb_saradc2_data().bits() as u16) & 0xfff
(sar_adc.sar2data_status().read().saradc2_data().bits() as u16) & 0xfff
}

fn reset() {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc
.int_clr()
.write(|w| w.apb_saradc2_done().clear_bit_by_one());
.write(|w| w.adc2_done().clear_bit_by_one());

sar_adc
.onetime_sample()
.modify(|_, w| w.saradc_onetime_start().clear_bit());
.modify(|_, w| w.onetime_start().clear_bit());
}

fn set_init_code(data: u16) {
Expand Down Expand Up @@ -416,14 +410,10 @@ where
PeripheralClockControl::enable(Peripheral::ApbSarAdc);

unsafe { &*APB_SARADC::PTR }.ctrl().modify(|_, w| unsafe {
w.saradc_start_force()
.set_bit()
.saradc_start()
.set_bit()
.saradc_sar_clk_gated()
.set_bit()
.saradc_xpd_sar_force()
.bits(0b11)
w.start_force().set_bit();
w.start().set_bit();
w.sar_clk_gated().set_bit();
w.xpd_sar_force().bits(0b11)
});

Adc {
Expand Down
24 changes: 3 additions & 21 deletions esp-hal/src/analog/adc/xtensa.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -238,15 +238,7 @@ impl RegisterAccess for crate::peripherals::ADC1 {
let adc = unsafe { &*APB_SARADC::ptr() };
let sensors = unsafe { &*SENS::ptr() };

cfg_if::cfg_if! {
if #[cfg(esp32s2)] {
adc.int_clr()
.write(|w| w.adc1_done().clear_bit_by_one());
} else {
adc.int_clr()
.write(|w| w.apb_saradc1_done().clear_bit_by_one());
}
}
adc.int_clr().write(|w| w.adc1_done().clear_bit_by_one());

sensors
.sar_meas1_ctrl2()
Expand Down Expand Up @@ -294,9 +286,7 @@ impl RegisterAccess for crate::peripherals::ADC2 {
.modify(|_, w| w.sar2_rtc_force().set_bit());

let sar_apb = unsafe { &*APB_SARADC::ptr() };
sar_apb
.arb_ctrl()
.modify(|_, w| w.adc_arb_rtc_force().set_bit());
sar_apb.arb_ctrl().modify(|_, w| w.rtc_force().set_bit());
}

fn set_start_force() {
Expand Down Expand Up @@ -362,15 +352,7 @@ impl RegisterAccess for crate::peripherals::ADC2 {
let adc = unsafe { &*APB_SARADC::ptr() };
let sensors = unsafe { &*SENS::ptr() };

cfg_if::cfg_if! {
if #[cfg(esp32s2)] {
adc.int_clr()
.write(|w| w.adc2_done().clear_bit_by_one());
} else {
adc.int_clr()
.write(|w| w.apb_saradc2_done().clear_bit_by_one());
}
}
adc.int_clr().write(|w| w.adc2_done().clear_bit_by_one());

sensors
.sar_meas2_ctrl2()
Expand Down

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