SPI: Implement interrupt-driven transfer_in_place_async (#2691)

* Implement transfer_async * The start of our shiny future * Add State * Wake from interrupt * Rename and remove return value * Fix register write * Fix S2 * Rename traits * Async flushes * Flush before async operations * Fix comments * Rename start fn, place async handler in RAM * Explicitly stop listening before async operations
esp-rs · Dec 18, 2024 · 2ca1545 · 2ca1545
1 parent f990957
commit 2ca1545
Show file tree

Hide file tree

Showing 3 changed files with 538 additions and 87 deletions.
diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -33,6 +33,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `BurstConfig`, a device-specific configuration for configuring DMA transfers in burst mode (#2543)
 - `{DmaRxBuf, DmaTxBuf, DmaRxTxBuf}::set_burst_config` (#2543)
 - ESP32-S2: DMA support for AES (#2699)
+- Added `transfer_in_place_async` and embedded-hal-async implementation to `Spi` (#2691)
 
 ### Changed