Same for C2/C3...

esp-rs · Feb 1, 2024 · 43eeb85 · 43eeb85
1 parent 3e0e8d2
commit 43eeb85
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Showing 11 changed files with 29 additions and 34 deletions.
diff --git a/esp-hal/src/analog/adc/calibration/curve.rs b/esp-hal/src/analog/adc/calibration/curve.rs
@@ -148,7 +148,7 @@ mod impls {
         #[cfg(esp32c3)]
         CURVES_COEFFS1 [
             Attenuation0dB => [
-                -0.2259664705000430,
+                -0.225966470500043,
                 -0.0007265418501948,
                 0.0000109410402681,
             ],
@@ -158,7 +158,7 @@ mod impls {
                 0.0000088166562521,
             ],
             Attenuation6dB => [
-                -1.0178592392364350,
+                -1.017859239236435,
                 -0.0097159265299153,
                 0.0000149794028038,
             ],

diff --git a/esp-hal/src/analog/adc/riscv.rs b/esp-hal/src/analog/adc/riscv.rs
@@ -557,7 +557,7 @@ where
     fn read(&mut self, pin: &mut AdcPin<PIN, ADCI, CS>) -> nb::Result<u16, Self::Error> {
         use embedded_hal::adc::Channel;
 
-        if self.attenuations[AdcPin::<PIN, ADCI>::channel() as usize] == None {
+        if self.attenuations[AdcPin::<PIN, ADCI>::channel() as usize].is_none() {
             panic!(
                 "Channel {} is not configured reading!",
                 AdcPin::<PIN, ADCI>::channel()

diff --git a/esp-hal/src/clock/clocks_ll/esp32c2.rs b/esp-hal/src/clock/clocks_ll/esp32c2.rs
@@ -49,9 +49,6 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
     let dchgp: u32;
     let dcur: u32;
     let dbias: u32;
-    let i2c_bbpll_lref: u32;
-    let i2c_bbpll_div_7_0: u32;
-    let i2c_bbpll_dcur: u32;
 
     unsafe {
         let clear_reg_mask = |reg, mask: u32| {
@@ -94,9 +91,10 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
 
     regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
 
-    i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
-    i2c_bbpll_div_7_0 = div7_0;
-    i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
+    let i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
+    let i2c_bbpll_div_7_0 = div7_0;
+    let i2c_bbpll_dcur =
+        (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
 
     regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
 

diff --git a/esp-hal/src/clock/clocks_ll/esp32c3.rs b/esp-hal/src/clock/clocks_ll/esp32c3.rs
@@ -53,9 +53,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
     let dchgp: u32;
     let dcur: u32;
     let dbias: u32;
-    let i2c_bbpll_lref: u32;
-    let i2c_bbpll_div_7_0: u32;
-    let i2c_bbpll_dcur: u32;
+
     unsafe {
         let clear_reg_mask = |reg, mask: u32| {
             (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !mask)
@@ -150,9 +148,10 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
         regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
     }
 
-    i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
-    i2c_bbpll_div_7_0 = div7_0;
-    i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
+    let i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
+    let i2c_bbpll_div_7_0 = div7_0;
+    let i2c_bbpll_dcur =
+        (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
 
     regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
 

diff --git a/esp-hal/src/gpio.rs b/esp-hal/src/gpio.rs
@@ -1750,38 +1750,38 @@ macro_rules! rtc_pins {
     (
         $pin_num:expr
     ) => {
-        impl<MODE> crate::gpio::RTCPin for GpioPin<MODE, $pin_num> {
+        impl<MODE> $crate::gpio::RTCPin for GpioPin<MODE, $pin_num> {
             unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
-                let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
+                let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() };
                 paste::paste! {
                     rtc_cntl.gpio_wakeup().modify(|_, w| w.[< gpio_pin $pin_num _wakeup_enable >]().bit(wakeup));
                     rtc_cntl.gpio_wakeup().modify(|_, w| w.[< gpio_pin $pin_num _int_type >]().bits(level));
                 }
             }
 
             fn rtcio_pad_hold(&mut self, enable: bool) {
-                let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
+                let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() };
                 paste::paste! {
                     rtc_cntl.pad_hold().modify(|_, w| w.[< gpio_pin $pin_num _hold >]().bit(enable));
                 }
             }
         }
 
-        impl<MODE> crate::gpio::RTCPinWithResistors for GpioPin<MODE, $pin_num> {
+        impl<MODE> $crate::gpio::RTCPinWithResistors for GpioPin<MODE, $pin_num> {
             fn rtcio_pullup(&mut self, enable: bool) {
-                let io_mux = unsafe { &*crate::peripherals::IO_MUX::ptr() };
+                let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() };
                 io_mux.gpio($pin_num).modify(|_, w| w.fun_wpu().bit(enable));
             }
 
             fn rtcio_pulldown(&mut self, enable: bool) {
-                let io_mux = unsafe { &*crate::peripherals::IO_MUX::ptr() };
+                let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() };
                 io_mux.gpio($pin_num).modify(|_, w| w.fun_wpd().bit(enable));
             }
         }
 
     };
 
-    ( $( $pin_num:expr )+ ) => { $( crate::gpio::rtc_pins!($pin_num); )+ };
+    ( $( $pin_num:expr )+ ) => { $( $crate::gpio::rtc_pins!($pin_num); )+ };
 }
 
 // Following code enables `into_analog`
@@ -1866,8 +1866,8 @@ macro_rules! analog {
         $($pin_num:literal)+
     ) => {
         pub(crate) fn internal_into_analog(pin: u8) {
-            use crate::peripherals::IO_MUX;
-            use crate::peripherals::GPIO;
+            use $crate::peripherals::IO_MUX;
+            use $crate::peripherals::GPIO;
 
             let io_mux = unsafe{ &*IO_MUX::PTR };
             let gpio = unsafe{ &*GPIO::PTR };

diff --git a/esp-hal/src/rsa/esp32cX.rs b/esp-hal/src/rsa/esp32cX.rs
@@ -31,7 +31,7 @@ impl<'d> Rsa<'d> {
     }
 
     fn write_mode(&mut self, mode: u32) {
-        self.rsa.mode().write(|w| unsafe { w.bits(mode as u32) });
+        self.rsa.mode().write(|w| unsafe { w.bits(mode) });
     }
 
     /// Enables/disables search acceleration, when enabled it would increases
@@ -106,11 +106,7 @@ impl<'d> Rsa<'d> {
     }
 
     unsafe fn write_multi_operand_b<const N: usize>(&mut self, operand_b: &[u32; N]) {
-        copy_nonoverlapping(
-            operand_b.as_ptr(),
-            self.rsa.z_mem(0).as_ptr().add(N) as *mut u32,
-            N,
-        );
+        copy_nonoverlapping(operand_b.as_ptr(), self.rsa.z_mem(0).as_ptr().add(N), N);
     }
 }
 

diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs
@@ -585,10 +585,10 @@ impl RtcSleepConfig {
                     .modify(|_, w| w.icache_tag_mem_force_on().clear_bit());
                 // clear register clock force on
                 // clear register clock force on
-                (&*esp32c3::SPI0::ptr())
+                (*esp32c3::SPI0::ptr())
                     .clock_gate()
                     .modify(|_, w| w.clk_en().clear_bit());
-                (&*esp32c3::SPI1::ptr())
+                (*esp32c3::SPI1::ptr())
                     .clock_gate()
                     .modify(|_, w| w.clk_en().clear_bit());
             }

diff --git a/esp-hal/src/soc/esp32c2/gpio.rs b/esp-hal/src/soc/esp32c2/gpio.rs
@@ -64,7 +64,7 @@ pub const ZERO_INPUT: u8 = 0x1f;
 pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
 
 pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
-    unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
+    unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
 }
 
 pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {

diff --git a/esp-hal/src/soc/esp32c2/mod.rs b/esp-hal/src/soc/esp32c2/mod.rs
@@ -13,6 +13,7 @@ pub mod gpio;
 pub mod peripherals;
 pub mod radio_clocks;
 
+#[allow(unused)]
 pub(crate) mod registers {
     pub const INTERRUPT_MAP_BASE: u32 = 0x600c2000;
 }

diff --git a/esp-hal/src/soc/esp32c3/gpio.rs b/esp-hal/src/soc/esp32c3/gpio.rs
@@ -65,7 +65,7 @@ pub const ZERO_INPUT: u8 = 0x1f;
 pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
 
 pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
-    unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
+    unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
 }
 
 pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {

diff --git a/esp-hal/src/soc/esp32c3/mod.rs b/esp-hal/src/soc/esp32c3/mod.rs
@@ -17,6 +17,7 @@ pub mod gpio;
 pub mod peripherals;
 pub mod radio_clocks;
 
+#[allow(unused)]
 pub(crate) mod registers {
     pub const INTERRUPT_MAP_BASE: u32 = 0x600c2000;
 }