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WIP (nggyp)
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@playfulFence
playfulFence committed Nov 14, 2024
1 parent 0ae4fb9 commit 6a401a4
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Showing 3 changed files with 118 additions and 93 deletions.
190 changes: 98 additions & 92 deletions esp-hal/src/interrupt/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -194,99 +194,100 @@ pub static RESERVED_INTERRUPTS: &[usize] = INTERRUPT_TO_PRIORITY;
#[link_section = ".trap.rust"]
#[export_name = "_start_trap_rust_hal"]
pub unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) {
// assert!(
// mcause::read().is_exception(),
// "Arrived into _start_trap_rust_hal but mcause is not an exception!"
// );

if riscv::register::mcause::read().is_exception() {
extern "C" {
fn ExceptionHandler(tf: *mut TrapFrame);
}
ExceptionHandler(trap_frame);
} else {
extern "C" {
fn interrupt1(frame: &mut TrapFrame);
fn interrupt2(frame: &mut TrapFrame);
fn interrupt3(frame: &mut TrapFrame);
fn interrupt4(frame: &mut TrapFrame);
fn interrupt5(frame: &mut TrapFrame);
fn interrupt6(frame: &mut TrapFrame);
fn interrupt7(frame: &mut TrapFrame);
fn interrupt8(frame: &mut TrapFrame);
fn interrupt9(frame: &mut TrapFrame);
fn interrupt10(frame: &mut TrapFrame);
fn interrupt11(frame: &mut TrapFrame);
fn interrupt12(frame: &mut TrapFrame);
fn interrupt13(frame: &mut TrapFrame);
fn interrupt14(frame: &mut TrapFrame);
fn interrupt15(frame: &mut TrapFrame);
fn interrupt16(frame: &mut TrapFrame);
fn interrupt17(frame: &mut TrapFrame);
fn interrupt18(frame: &mut TrapFrame);
fn interrupt19(frame: &mut TrapFrame);
fn interrupt20(frame: &mut TrapFrame);
fn interrupt21(frame: &mut TrapFrame);
fn interrupt22(frame: &mut TrapFrame);
fn interrupt23(frame: &mut TrapFrame);
fn interrupt24(frame: &mut TrapFrame);
fn interrupt25(frame: &mut TrapFrame);
fn interrupt26(frame: &mut TrapFrame);
fn interrupt27(frame: &mut TrapFrame);
fn interrupt28(frame: &mut TrapFrame);
fn interrupt29(frame: &mut TrapFrame);
fn interrupt30(frame: &mut TrapFrame);
fn interrupt31(frame: &mut TrapFrame);

// Defined in `esp-riscv-rt`
pub fn DefaultHandler();
}

let interrupt_priority = _handle_priority();

let code = riscv::register::mcause::read().code();

// #[cfg(clic)]
let code = (code & 0b1111_1111_1111) - 16 as usize;

match code {
1 => interrupt1(trap_frame.as_mut().unwrap()),
2 => interrupt2(trap_frame.as_mut().unwrap()),
3 => interrupt3(trap_frame.as_mut().unwrap()),
4 => interrupt4(trap_frame.as_mut().unwrap()),
5 => interrupt5(trap_frame.as_mut().unwrap()),
6 => interrupt6(trap_frame.as_mut().unwrap()),
7 => interrupt7(trap_frame.as_mut().unwrap()),
8 => interrupt8(trap_frame.as_mut().unwrap()),
9 => interrupt9(trap_frame.as_mut().unwrap()),
10 => interrupt10(trap_frame.as_mut().unwrap()),
11 => interrupt11(trap_frame.as_mut().unwrap()),
12 => interrupt12(trap_frame.as_mut().unwrap()),
13 => interrupt13(trap_frame.as_mut().unwrap()),
14 => interrupt14(trap_frame.as_mut().unwrap()),
15 => interrupt15(trap_frame.as_mut().unwrap()),
16 => interrupt16(trap_frame.as_mut().unwrap()),
17 => interrupt17(trap_frame.as_mut().unwrap()),
18 => interrupt18(trap_frame.as_mut().unwrap()),
19 => interrupt19(trap_frame.as_mut().unwrap()),
20 => interrupt20(trap_frame.as_mut().unwrap()),
21 => interrupt21(trap_frame.as_mut().unwrap()),
22 => interrupt22(trap_frame.as_mut().unwrap()),
23 => interrupt23(trap_frame.as_mut().unwrap()),
24 => interrupt24(trap_frame.as_mut().unwrap()),
25 => interrupt25(trap_frame.as_mut().unwrap()),
26 => interrupt26(trap_frame.as_mut().unwrap()),
27 => interrupt27(trap_frame.as_mut().unwrap()),
28 => interrupt28(trap_frame.as_mut().unwrap()),
29 => interrupt29(trap_frame.as_mut().unwrap()),
30 => interrupt30(trap_frame.as_mut().unwrap()),
31 => interrupt31(trap_frame.as_mut().unwrap()),
_ => DefaultHandler(),
};

_restore_priority(interrupt_priority);
// FIXME: esp32p4 get here even when interrupt is not jumping to the vec
// handlers from esp-riscv-rt
assert!(
mcause::read().is_exception(),
"Arrived into _start_trap_rust_hal but mcause is not an exception!"
);

// if riscv::register::mcause::read().is_exception() {
extern "C" {
fn ExceptionHandler(tf: *mut TrapFrame);
}

ExceptionHandler(trap_frame);
// } else {
// extern "C" {
// fn interrupt1(frame: &mut TrapFrame);
// fn interrupt2(frame: &mut TrapFrame);
// fn interrupt3(frame: &mut TrapFrame);
// fn interrupt4(frame: &mut TrapFrame);
// fn interrupt5(frame: &mut TrapFrame);
// fn interrupt6(frame: &mut TrapFrame);
// fn interrupt7(frame: &mut TrapFrame);
// fn interrupt8(frame: &mut TrapFrame);
// fn interrupt9(frame: &mut TrapFrame);
// fn interrupt10(frame: &mut TrapFrame);
// fn interrupt11(frame: &mut TrapFrame);
// fn interrupt12(frame: &mut TrapFrame);
// fn interrupt13(frame: &mut TrapFrame);
// fn interrupt14(frame: &mut TrapFrame);
// fn interrupt15(frame: &mut TrapFrame);
// fn interrupt16(frame: &mut TrapFrame);
// fn interrupt17(frame: &mut TrapFrame);
// fn interrupt18(frame: &mut TrapFrame);
// fn interrupt19(frame: &mut TrapFrame);
// fn interrupt20(frame: &mut TrapFrame);
// fn interrupt21(frame: &mut TrapFrame);
// fn interrupt22(frame: &mut TrapFrame);
// fn interrupt23(frame: &mut TrapFrame);
// fn interrupt24(frame: &mut TrapFrame);
// fn interrupt25(frame: &mut TrapFrame);
// fn interrupt26(frame: &mut TrapFrame);
// fn interrupt27(frame: &mut TrapFrame);
// fn interrupt28(frame: &mut TrapFrame);
// fn interrupt29(frame: &mut TrapFrame);
// fn interrupt30(frame: &mut TrapFrame);
// fn interrupt31(frame: &mut TrapFrame);

// // Defined in `esp-riscv-rt`
// pub fn DefaultHandler();
// }

// let interrupt_priority = _handle_priority();

// let code = riscv::register::mcause::read().code();

// // #[cfg(clic)]
// let code = (code & 0b1111_1111_1111) - 16 as usize;

// match code {
// 1 => interrupt1(trap_frame.as_mut().unwrap()),
// 2 => interrupt2(trap_frame.as_mut().unwrap()),
// 3 => interrupt3(trap_frame.as_mut().unwrap()),
// 4 => interrupt4(trap_frame.as_mut().unwrap()),
// 5 => interrupt5(trap_frame.as_mut().unwrap()),
// 6 => interrupt6(trap_frame.as_mut().unwrap()),
// 7 => interrupt7(trap_frame.as_mut().unwrap()),
// 8 => interrupt8(trap_frame.as_mut().unwrap()),
// 9 => interrupt9(trap_frame.as_mut().unwrap()),
// 10 => interrupt10(trap_frame.as_mut().unwrap()),
// 11 => interrupt11(trap_frame.as_mut().unwrap()),
// 12 => interrupt12(trap_frame.as_mut().unwrap()),
// 13 => interrupt13(trap_frame.as_mut().unwrap()),
// 14 => interrupt14(trap_frame.as_mut().unwrap()),
// 15 => interrupt15(trap_frame.as_mut().unwrap()),
// 16 => interrupt16(trap_frame.as_mut().unwrap()),
// 17 => interrupt17(trap_frame.as_mut().unwrap()),
// 18 => interrupt18(trap_frame.as_mut().unwrap()),
// 19 => interrupt19(trap_frame.as_mut().unwrap()),
// 20 => interrupt20(trap_frame.as_mut().unwrap()),
// 21 => interrupt21(trap_frame.as_mut().unwrap()),
// 22 => interrupt22(trap_frame.as_mut().unwrap()),
// 23 => interrupt23(trap_frame.as_mut().unwrap()),
// 24 => interrupt24(trap_frame.as_mut().unwrap()),
// 25 => interrupt25(trap_frame.as_mut().unwrap()),
// 26 => interrupt26(trap_frame.as_mut().unwrap()),
// 27 => interrupt27(trap_frame.as_mut().unwrap()),
// 28 => interrupt28(trap_frame.as_mut().unwrap()),
// 29 => interrupt29(trap_frame.as_mut().unwrap()),
// 30 => interrupt30(trap_frame.as_mut().unwrap()),
// 31 => interrupt31(trap_frame.as_mut().unwrap()),
// _ => DefaultHandler(),
// };

// _restore_priority(interrupt_priority);
// }
}

#[doc(hidden)]
Expand All @@ -313,6 +314,11 @@ pub fn _setup_interrupts() {
let vec_table = &_vector_table as *const _ as usize;
mtvec::write(vec_table, mtvec::TrapMode::Vectored);

// 0x307 - MTVT address
unsafe {
core::arch::asm!("csrw 0x307, {0}", in(reg) vec_table);
}

crate::interrupt::init_vectoring();
};

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19 changes: 19 additions & 0 deletions esp-riscv-rt/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -799,7 +799,26 @@ abort:
.option norelax
.option norvc
// P4: System Interrupts definitions
// https://github.com/espressif/esp-idf/blob/master/components/riscv/vectors_clic.S#L74
_vector_table:
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap_rust_hal
j _start_trap
j _start_trap1
j _start_trap2
Expand Down
2 changes: 1 addition & 1 deletion examples/src/bin/software_interrupts.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
//! Should rotate through all of the available interrupts printing their number
//! when raised.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32p4 esp32s2 esp32s3

#![no_std]
#![no_main]
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