Fix test

esp-hal/src/dma/buffers.rs

@@ -345,6 +345,8 @@ pub enum TransferDirection {
 }
 
 /// Holds all the information needed to configure a DMA channel for a transfer.
+#[derive(PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Preparation {
     /// The descriptor the DMA will start from.
     pub start: *mut DmaDescriptor,

esp-hal/src/dma/mod.rs

@@ -1908,6 +1908,9 @@ where
     ) -> Result<(), DmaError> {
         debug_assert_eq!(preparation.direction, TransferDirection::In);
 
+        debug!("Preparing RX transfer {:?}", preparation);
+        trace!("First descriptor {:?}", unsafe { &*preparation.start });
+
         #[cfg(psram_dma)]
         if preparation.accesses_psram && !self.rx_impl.can_access_psram() {
             return Err(DmaError::UnsupportedMemoryRegion);
@@ -2199,6 +2202,9 @@ where
     ) -> Result<(), DmaError> {
         debug_assert_eq!(preparation.direction, TransferDirection::Out);
 
+        debug!("Preparing TX transfer {:?}", preparation);
+        trace!("First descriptor {:?}", unsafe { &*preparation.start });
+
         #[cfg(psram_dma)]
         if preparation.accesses_psram && !self.tx_impl.can_access_psram() {
             return Err(DmaError::UnsupportedMemoryRegion);

hil-test/tests/spi_full_duplex.rs

@@ -197,6 +197,9 @@ mod tests {
         unit.channel0
             .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
 
+        dma_rx_buf.set_length(TRANSFER_SIZE);
+        dma_tx_buf.set_length(TRANSFER_SIZE);
+
         // Fill the buffer where each byte has 3 pos edges.
         dma_tx_buf.as_mut_slice().fill(0b0110_1010);
 
@@ -234,6 +237,9 @@ mod tests {
         unit.channel0
             .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
 
+        dma_rx_buf.set_length(TRANSFER_SIZE);
+        dma_tx_buf.set_length(TRANSFER_SIZE);
+
         // Fill the buffer where each byte has 3 pos edges.
         dma_tx_buf.as_mut_slice().fill(0b0110_1010);