Always enable burst transfering descriptors

esp-hal/src/dma/gdma.rs

@@ -170,10 +170,15 @@ impl<C: GdmaChannel> RegisterAccess for ChannelTxImpl<C> {
     }
 
     fn set_burst_mode(&self, burst_mode: bool) {
-        self.ch().out_conf0().modify(|_, w| {
-            w.out_data_burst_en().bit(burst_mode);
-            w.outdscr_burst_en().bit(burst_mode)
-        });
+        self.ch()
+            .out_conf0()
+            .modify(|_, w| w.out_data_burst_en().bit(burst_mode));
+    }
+
+    fn set_descr_burst_mode(&self, burst_mode: bool) {
+        self.ch()
+            .out_conf0()
+            .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
     }
 
     fn set_priority(&self, priority: DmaPriority) {
@@ -389,10 +394,15 @@ impl<C: GdmaChannel> RegisterAccess for ChannelRxImpl<C> {
     }
 
     fn set_burst_mode(&self, burst_mode: bool) {
-        self.ch().in_conf0().modify(|_, w| {
-            w.in_data_burst_en().bit(burst_mode);
-            w.indscr_burst_en().bit(burst_mode)
-        });
+        self.ch()
+            .in_conf0()
+            .modify(|_, w| w.in_data_burst_en().bit(burst_mode));
+    }
+
+    fn set_descr_burst_mode(&self, burst_mode: bool) {
+        self.ch()
+            .in_conf0()
+            .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
     }
 
     fn set_priority(&self, priority: DmaPriority) {

esp-hal/src/dma/mod.rs

@@ -1820,6 +1820,7 @@ where
         let preparation = buffer.prepare();
 
         self.rx_impl.set_burst_mode(false);
+        self.rx_impl.set_descr_burst_mode(true);
         self.rx_impl.set_check_owner(preparation.check_owner);
 
         compiler_fence(core::sync::atomic::Ordering::SeqCst);
@@ -2108,6 +2109,7 @@ where
         );
 
         self.tx_impl.set_burst_mode(false);
+        self.tx_impl.set_descr_burst_mode(true);
         self.tx_impl.set_check_owner(preparation.check_owner);
 
         compiler_fence(core::sync::atomic::Ordering::SeqCst);
@@ -2181,9 +2183,13 @@ pub trait RegisterAccess: crate::private::Sealed {
     fn reset(&self);
 
     /// Enable/Disable INCR burst transfer for channel reading
-    /// descriptor and accessing data in internal RAM.
+    /// accessing data in internal RAM.
     fn set_burst_mode(&self, burst_mode: bool);
 
+    /// Enable/Disable burst transfer for channel reading
+    /// descriptors in internal RAM.
+    fn set_descr_burst_mode(&self, burst_mode: bool);
+
     /// The priority of the channel. The larger the value, the higher the
     /// priority.
     #[cfg(gdma)]

esp-hal/src/dma/pdma.rs

@@ -58,6 +58,12 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> RegisterAccess for SpiDma
     }
 
     fn set_burst_mode(&self, burst_mode: bool) {
+        let spi = self.0.register_block();
+        spi.dma_conf()
+            .modify(|_, w| w.out_data_burst_en().bit(burst_mode));
+    }
+
+    fn set_descr_burst_mode(&self, burst_mode: bool) {
         let spi = self.0.register_block();
         spi.dma_conf()
             .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
@@ -216,7 +222,9 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> RegisterAccess for SpiDma
         spi.dma_conf().modify(|_, w| w.in_rst().clear_bit());
     }
 
-    fn set_burst_mode(&self, burst_mode: bool) {
+    fn set_burst_mode(&self, _burst_mode: bool) {}
+
+    fn set_descr_burst_mode(&self, burst_mode: bool) {
         let spi = self.0.register_block();
         spi.dma_conf()
             .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
@@ -466,17 +474,24 @@ pub struct I2sDmaTxChannelImpl<C>(C);
 impl<C> crate::private::Sealed for I2sDmaTxChannelImpl<C> {}
 
 impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> RegisterAccess for I2sDmaTxChannelImpl<C> {
+    fn reset(&self) {
+        let reg_block = self.0.register_block();
+        reg_block.lc_conf().modify(|_, w| w.out_rst().set_bit());
+        reg_block.lc_conf().modify(|_, w| w.out_rst().clear_bit());
+    }
+
     fn set_burst_mode(&self, burst_mode: bool) {
         let reg_block = self.0.register_block();
         reg_block
             .lc_conf()
-            .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
+            .modify(|_, w| w.out_data_burst_en().bit(burst_mode));
     }
 
-    fn reset(&self) {
+    fn set_descr_burst_mode(&self, burst_mode: bool) {
         let reg_block = self.0.register_block();
-        reg_block.lc_conf().modify(|_, w| w.out_rst().set_bit());
-        reg_block.lc_conf().modify(|_, w| w.out_rst().clear_bit());
+        reg_block
+            .lc_conf()
+            .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
     }
 
     fn set_link_addr(&self, address: u32) {
@@ -638,19 +653,21 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaTxInte
 }
 
 impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> RegisterAccess for I2sDmaRxChannelImpl<C> {
-    fn set_burst_mode(&self, burst_mode: bool) {
-        let reg_block = self.0.register_block();
-        reg_block
-            .lc_conf()
-            .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
-    }
-
     fn reset(&self) {
         let reg_block = self.0.register_block();
         reg_block.lc_conf().modify(|_, w| w.in_rst().set_bit());
         reg_block.lc_conf().modify(|_, w| w.in_rst().clear_bit());
     }
 
+    fn set_burst_mode(&self, _burst_mode: bool) {}
+
+    fn set_descr_burst_mode(&self, burst_mode: bool) {
+        let reg_block = self.0.register_block();
+        reg_block
+            .lc_conf()
+            .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
+    }
+
     fn set_link_addr(&self, address: u32) {
         let reg_block = self.0.register_block();
         reg_block