Merge branch 'main' into fugit-delay

.github/PULL_REQUEST_TEMPLATE.md

@@ -1,18 +1,18 @@
-## Thank you!
+## Thank you for your contribution!
 
-Thank you for your contribution.
-Please make sure that your submission includes the following:
+We appreciate the time and effort you've put into this pull request.
+To help us review it efficiently, please ensure you've gone through the following checklist:
 
-### Must
+### Submission Checklist 📝
+- [ ] I have updated existing examples or added new ones (if applicable).
+- [ ] My changes were added to the [`CHANGELOG.md`](https://github.com/esp-rs/esp-hal/blob/main/esp-hal/CHANGELOG.md) in the **_proper_** section.
+#### Extra:
+- [ ] I have read the [CONTRIBUTING.md guide](https://github.com/esp-rs/esp-hal/blob/main/CONTRIBUTING.md) and followed its instructions.
 
-- [ ] The code compiles without `errors` or `warnings`.
-- [ ] All examples work.
-- [ ] `cargo fmt` was run.
-- [ ] Your changes were added to the `CHANGELOG.md` in the proper section.
-- [ ] You updated existing examples or added examples (if applicable).
-- [ ] Added examples are checked in CI
+### Pull Request Details 📖
 
-### Nice to have
+#### Description
+Please provide a clear and concise description of your changes, including the motivation behind these changes. The context is crucial for the reviewers.
 
-- [ ] You add a description of your work to this PR.
-- [ ] You added proper docs for your newly added features and code.
+#### Testing
+Describe how you tested your changes.

.github/workflows/ci.yml

@@ -56,7 +56,7 @@ jobs:
             "esp32c3",
             "esp32c6",
             "esp32h2",
-            "esp32p4",
+            # "esp32p4",
             # Xtensa devices:
             "esp32",
             "esp32s2",
@@ -179,7 +179,7 @@ jobs:
           cargo xtask build-package --features=esp32c3 --target=riscv32imc-unknown-none-elf   esp-hal
           cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf  esp-hal
           cargo xtask build-package --features=esp32h2 --target=riscv32imac-unknown-none-elf  esp-hal
-          cargo xtask build-package --features=esp32p4 --target=riscv32imafc-unknown-none-elf esp-hal
+      #   cargo xtask build-package --features=esp32p4 --target=riscv32imafc-unknown-none-elf esp-hal
       - name: msrv (esp-lp-hal)
         run: |
           cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf esp-lp-hal

esp-hal/CHANGELOG.md

@@ -9,24 +9,29 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Added
 
+- ESP32-C6 / ESP32-H2: Implement `ETM` for general purpose timers (#1274)
+- `interrupt::enable` now has a direct CPU enable counter part, `interrupt::enable_direct` (#1310)
 - `Delay::delay(time: fugit::MicrosDurationU64)`
 
 ### Fixed
 
 - Reserve `esp32` ROM stacks to prevent the trashing of dram2 section (#1289)
 - Fixing `esp-wifi` + `TRNG` issue on `ESP32-S2` (#1272)
 - Fixed core1 startup using the wrong stack on the esp32 and esp32s3 (#1286).
+- ESP32: Apply fix for Errata 3.6 in all the places necessary. (#1315)
 
 ### Changed
 
 - Remove `Ext32` and `RateExtU64` from prelude
 - Prefer mutable references over moving for DMA transactions (#1238)
 - Support runtime interrupt binding, adapt GPIO driver (#1231)
 - Renamed `eh1` feature to `embedded-hal`, feature-gated `[email protected]` trait implementations (#1273)
+- Enable `embedded-hal` feature by default, instead of the `embedded-hal-02` feature (#1313)
 
 ### Removed
 
 - Remove package-level type exports (#1275)
+- Removed `direct-vectoring` & `interrupt-preemption` features, as they are now enabled by default (#1310)
 
 ## [0.16.1] - 2024-03-12
 

esp-hal/Cargo.toml

@@ -74,7 +74,7 @@ esp-metadata = { version = "0.1.0", path = "../esp-metadata" }
 serde        = { version = "1.0.197", features = ["derive"] }
 
 [features]
-default = ["embedded-hal-02", "rt", "vectored"]
+default = ["embedded-hal", "rt", "vectored"]
 
 riscv  = ["dep:riscv",     "critical-section/restore-state-u8",  "esp-riscv-rt?/zero-bss"]
 xtensa = ["dep:xtensa-lx", "critical-section/restore-state-u32"]
@@ -111,35 +111,31 @@ rt = [
 ]
 ## Enable interrupt vectoring.
 vectored = ["procmacros/interrupt"]
+## Configuration for placing device drivers in the IRAM for faster access.
+place-spi-driver-in-ram = []
 
-#! ### Chip Support Feature Flags
-## Target the ESP32.
+# Chip Support Feature Flags
+# Target the ESP32.
 esp32   = ["dep:esp32",   "xtensa", "xtensa-lx/spin", "xtensa-lx-rt?/esp32"]
-## Target the ESP32-C2.
+# Target the ESP32-C2.
 esp32c2 = ["dep:esp32c2", "riscv",  "portable-atomic/unsafe-assume-single-core"]
-## Target the ESP32-C3.
+# Target the ESP32-C3.
 esp32c3 = ["dep:esp32c3", "riscv",  "portable-atomic/unsafe-assume-single-core", "rv-zero-rtc-bss"]
-## Target the ESP32-C6.
+# Target the ESP32-C6.
 esp32c6 = ["dep:esp32c6", "riscv",  "procmacros/has-lp-core", "rv-zero-rtc-bss"]
-## Target the ESP32-H2.
+# Target the ESP32-H2.
 esp32h2 = ["dep:esp32h2", "riscv", "rv-zero-rtc-bss"]
-## Target the ESP32-P4.
+# Target the ESP32-P4.
 esp32p4 = ["dep:esp32p4", "riscv",  "procmacros/has-lp-core", "rv-zero-rtc-bss"]
-## Target the ESP32-S2.
+# Target the ESP32-S2.
 esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt?/esp32s2", "usb-otg"]
-## Target the ESP32-S3.
+# Target the ESP32-S3.
 esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx/spin", "xtensa-lx-rt?/esp32s3", "usb-otg"]
 
 #! ### RISC-V Exclusive Feature Flags
-## Enable direct interrupt vectoring.
-direct-vectoring = ["esp-riscv-rt/direct-vectoring"]
 ## Move the stack to start of RAM to get zero-cost stack overflow protection
 ## (ESP32-C6 and ESPS32-H2 only!).
 flip-link = ["esp-riscv-rt/fix-sp"]
-## Enable interrupt preemption.
-interrupt-preemption = ["esp-riscv-rt/interrupt-preemption"]
-## Configuration for placing device drivers in the IRAM for faster access.
-place-spi-driver-in-ram = []
 ## Initialize the `.data` section of memory.
 rv-init-data = ["esp-riscv-rt?/init-data", "esp-riscv-rt?/init-rw-text"]
 ## Zero the `.bss` section of low-power memory.
@@ -168,11 +164,11 @@ defmt = [
     "embedded-io/defmt-03",
     "embedded-io-async?/defmt-03",
 ]
-## Implement the traits defined in the `0.2.x` release of `embedded-hal`.
-embedded-hal-02 = ["dep:embedded-hal-02"]
 ## Implement the traits defined in the `1.0.0` releases of `embedded-hal` and
 ## `embedded-hal-nb` for the relevant peripherals.
 embedded-hal = ["dep:embedded-hal", "dep:embedded-hal-nb", "dep:embedded-can"]
+## Implement the traits defined in the `0.2.x` release of `embedded-hal`.
+embedded-hal-02 = ["dep:embedded-hal-02"]
 ## Implement the traits defined in `embedded-io` for certain peripherals.
 embedded-io = ["dep:embedded-io"]
 ## Implement the `ufmt_write::uWrite` trait for certain peripherals.
@@ -221,6 +217,14 @@ opsram-8m = []
 ## Use externally connected Octal RAM (16MB).
 opsram-16m = []
 
+# This feature is intended for testing; you probably don't want to enable it:
+ci = [
+    "default",
+    "embedded-hal-02",
+    "ufmt",
+    "async",
+]
+
 [lints.clippy]
 mixed_attributes_style = "allow"
 

esp-hal/build.rs

@@ -7,7 +7,7 @@ use std::{
     str::FromStr,
 };
 
-use esp_metadata::{Arch, Chip, Config};
+use esp_metadata::{Chip, Config};
 
 // Macros taken from:
 // https://github.com/TheDan64/inkwell/blob/36c3b10/src/lib.rs#L81-L110
@@ -113,21 +113,13 @@ fn main() -> Result<(), Box<dyn Error>> {
         panic!("The target does not support PSRAM");
     }
 
-    // Don't support "interrupt-preemption" and "direct-vectoring" on Xtensa and
-    // RISC-V with CLIC:
-    if (config.contains(&String::from("clic")) || config.arch() == Arch::Xtensa)
-        && (cfg!(feature = "direct-vectoring") || cfg!(feature = "interrupt-preemption"))
-    {
-        panic!("The target does not support interrupt-preemption and direct-vectoring");
-    }
-
     // Define all necessary configuration symbols for the configured device:
     config.define_symbols();
 
     #[allow(unused_mut)]
     let mut config_symbols = config.all();
     #[cfg(feature = "flip-link")]
-    config_symbols.push("flip-link");
+    config_symbols.push("flip-link".to_owned());
 
     // Place all linker scripts in `OUT_DIR`, and instruct Cargo how to find these
     // files:

esp-hal/src/analog/adc/esp32.rs

@@ -249,7 +249,9 @@ impl RegisterAccess for ADC2 {
 /// Analog-to-Digital Converter peripheral driver.
 pub struct ADC<'d, ADC> {
     _adc: PeripheralRef<'d, ADC>,
+    #[allow(dead_code)] // FIXME
     attenuations: [Option<Attenuation>; 10],
+    #[allow(dead_code)] // FIXME
     active_channel: Option<u8>,
 }
 
@@ -418,6 +420,7 @@ macro_rules! impl_adc_interface {
 }
 
 mod adc_implementation {
+    #[cfg(feature = "embedded-hal-02")]
     use crate::peripherals::{ADC1, ADC2};
 
     impl_adc_interface! {

esp-hal/src/analog/adc/riscv.rs

@@ -486,7 +486,9 @@ impl CalibrationAccess for crate::peripherals::ADC2 {
 /// Analog-to-Digital Converter peripheral driver.
 pub struct ADC<'d, ADCI> {
     _adc: PeripheralRef<'d, ADCI>,
+    #[allow(dead_code)] // FIXME
     attenuations: [Option<Attenuation>; NUM_ATTENS],
+    #[allow(dead_code)] // FIXME
     active_channel: Option<u8>,
 }
 
@@ -648,6 +650,7 @@ macro_rules! impl_adc_interface {
 
 #[cfg(esp32c2)]
 mod adc_implementation {
+    #[cfg(feature = "embedded-hal-02")]
     use crate::peripherals::ADC1;
 
     impl_adc_interface! {
@@ -663,6 +666,7 @@ mod adc_implementation {
 
 #[cfg(esp32c3)]
 mod adc_implementation {
+    #[cfg(feature = "embedded-hal-02")]
     use crate::peripherals::{ADC1, ADC2};
 
     impl_adc_interface! {
@@ -684,6 +688,7 @@ mod adc_implementation {
 
 #[cfg(esp32c6)]
 mod adc_implementation {
+    #[cfg(feature = "embedded-hal-02")]
     use crate::peripherals::ADC1;
 
     impl_adc_interface! {
@@ -701,6 +706,7 @@ mod adc_implementation {
 
 #[cfg(esp32h2)]
 mod adc_implementation {
+    #[cfg(feature = "embedded-hal-02")]
     use crate::peripherals::ADC1;
 
     impl_adc_interface! {

esp-hal/src/analog/adc/xtensa.rs

@@ -524,7 +524,9 @@ impl CalibrationAccess for crate::peripherals::ADC2 {
 /// Analog-to-Digital Converter peripheral driver.
 pub struct ADC<'d, ADC> {
     _adc: PeripheralRef<'d, ADC>,
+    #[allow(dead_code)] // FIXME
     attenuations: [Option<Attenuation>; 10],
+    #[allow(dead_code)] // FIXME
     active_channel: Option<u8>,
 }
 
@@ -719,6 +721,7 @@ macro_rules! impl_adc_interface {
 }
 
 mod adc_implementation {
+    #[cfg(feature = "embedded-hal-02")]
     use crate::peripherals::{ADC1, ADC2};
 
     impl_adc_interface! {

esp-hal/src/embassy/executor/interrupt.rs

@@ -42,11 +42,7 @@ macro_rules! from_cpu {
                         panic!("FROM_CPU_{} is already used by a different executor.", $irq);
                     }
 
-                    // unsafe block because of direct-vectoring on riscv
-                    #[allow(unused_unsafe)]
-                    unsafe {
-                        unwrap!(interrupt::enable(peripherals::Interrupt::[<FROM_CPU_INTR $irq>], priority));
-                    }
+                    unwrap!(interrupt::enable(peripherals::Interrupt::[<FROM_CPU_INTR $irq>], priority));
                 }
 
                 fn number() -> usize {

esp-hal/src/gpio.rs

@@ -622,7 +622,7 @@ where
             .modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) });
 
         #[cfg(esp32)]
-        crate::soc::gpio::errata36(GPIONUM, pull_up, pull_down);
+        crate::soc::gpio::errata36(GPIONUM, Some(pull_up), Some(pull_down));
 
         // NOTE: Workaround to make GPIO18 and GPIO19 work on the ESP32-C3, which by
         //       default are assigned to the `USB_SERIAL_JTAG` peripheral.
@@ -1139,6 +1139,9 @@ where
     fn init_output(&self, alternate: AlternateFunction, open_drain: bool) {
         let gpio = unsafe { &*GPIO::PTR };
 
+        #[cfg(esp32)]
+        crate::soc::gpio::errata36(GPIONUM, Some(false), Some(false));
+
         <Self as GpioProperties>::Bank::write_out_en_set(1 << (GPIONUM % 32));
         gpio.pin(GPIONUM as usize)
             .modify(|_, w| w.pad_driver().bit(open_drain));
@@ -1277,10 +1280,16 @@ where
     }
 
     fn internal_pull_up(&mut self, on: bool) -> &mut Self {
+        #[cfg(esp32)]
+        crate::soc::gpio::errata36(GPIONUM, Some(on), None);
+
         get_io_mux_reg(GPIONUM).modify(|_, w| w.fun_wpu().bit(on));
         self
     }
     fn internal_pull_down(&mut self, on: bool) -> &mut Self {
+        #[cfg(esp32)]
+        crate::soc::gpio::errata36(GPIONUM, None, Some(on));
+
         get_io_mux_reg(GPIONUM).modify(|_, w| w.fun_wpd().bit(on));
         self
     }

esp-hal/src/i2c.rs

@@ -255,10 +255,10 @@ where
         self.peripheral.master_write_read(address, bytes, buffer)
     }
 
-    fn transaction<'a>(
+    fn transaction(
         &mut self,
         _address: u8,
-        _operations: &mut [embedded_hal::i2c::Operation<'a>],
+        _operations: &mut [embedded_hal::i2c::Operation<'_>],
     ) -> Result<(), Self::Error> {
         todo!()
     }

esp-hal/src/interrupt/mod.rs

@@ -1,27 +1,18 @@
 //! # Interrupt support
 //!
-//! ## Overview
-//! The `interrupt` driver is a crucial module for ESP chips. Its primary
-//! purpose is to manage and handle interrupts, which are asynchronous events
-//! requiring immediate attention from the CPU. Interrupts are essential in
-//! various applications, such as real-time tasks, I/O communications, and
-//! handling external events like hardware signals.
-//!
-//! The core functionality of the `interrupt` driver revolves around the
-//! management of interrupts. When an interrupt occurs, it temporarily stops the
-//! ongoing CPU operations, saves its current state, and starts executing the
-//! corresponding interrupt service routine (ISR). The interrupt service routine
-//! is a user-defined function that performs the necessary actions to handle the
-//! specific interrupt. Once the ISR is executed, the driver restores the saved
-//! CPU state and resumes normal program execution.
-//!
-//! In scenarios where multiple interrupts may occur simultaneously, the
-//! interrupt driver determines the `priority` of each interrupt. This
-//! prioritization ensures that critical or high-priority tasks are handled
-//! first. It helps prevent delays in time-sensitive applications and allows the
-//! system to allocate resources efficiently. This functionality is provided and
-//! implemented by the `priority` enum.
+//! Interrupt support functionality depends heavily on the features enabled.
 //!
+//! When the `vectored` feature is enabled, the
+//! [`enable`] method will map interrupt to a CPU
+//! interrupt, and handle the `vector`ing to the peripheral interrupt, for
+//! example `UART0`.
+//!
+//! It is also possible, but not recommended, to bind an interrupt directly to a
+//! CPU interrupt. This can offer lower latency, at the cost of more complexity
+//! in the interrupt handler.
+//!
+//! The `vectored` reserves a number of CPU interrupts, which cannot be used see
+//! [`RESERVED_INTERRUPTS`].
 //!
 //! ## Example
 //! ```no_run
@@ -30,12 +21,20 @@
 //!     ...
 //!     critical_section::with(|cs| SWINT.borrow_ref_mut(cs).replace(sw_int));
 //!
+//!     // enable the interrupt
 //!     interrupt::enable(
 //!         peripherals::Interrupt::FROM_CPU_INTR0,
 //!         interrupt::Priority::Priority1,
 //!     )
 //!     .unwrap();
 //!
+//!     // trigger the interrupt
+//!     SWINT
+//!        .borrow_ref_mut(cs)
+//!        .as_mut()
+//!        .unwrap()
+//!        .raise(SoftwareInterrupt::SoftwareInterrupt0);
+//!
 //!     loop {}
 //! }
 //!