RISC-V chips (except P4) now pass clippy in CI

.github/workflows/ci.yml

@@ -709,11 +709,32 @@ jobs:
       - uses: dtolnay/rust-toolchain@v1
         with:
           toolchain: nightly
-          targets: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          targets: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf # ,riscv32imafc-unknown-none-elf
           components: clippy,rust-src
       - uses: Swatinem/rust-cache@v2
 
       # Run 'cargo clippy' on all packages targeting RISC-V:
+      - name: clippy (esp32c2-hal)
+        run: |
+          cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=esp32c2,xtal-40mhz \
+            -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default
+      - name: clippy (esp32c3-hal)
+        run: |
+          cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=esp32c3 \
+            -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default
+      - name: clippy (esp32c6-hal)
+        run: |
+          cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imac-unknown-none-elf --features=esp32c6 \
+            -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default
+      - name: clippy (esp32h2-hal)
+        run: |
+          cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imac-unknown-none-elf --features=esp32h2 \
+            -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default
+      # - name: clippy (esp32p4-hal)
+      #   run: |
+      #     cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imafc-unknown-none-elf --features=esp32p4 \
+      #       -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default
+
       - name: clippy (esp-lp-hal, esp32c6)
         run: cd esp-lp-hal && cargo clippy --features=esp32c6 -- -D warnings
       - name: clippy (esp-lp-hal, esp32s2)
@@ -722,16 +743,6 @@ jobs:
         run: cd esp-lp-hal && cargo clippy --features=esp32s3 -- -D warnings
       - name: clippy (esp-riscv-rt)
         run: cd esp-riscv-rt && cargo clippy --target=riscv32imc-unknown-none-elf -- -D warnings
-      - name: clippy (esp32c2-hal)
-        run: cd esp32c2-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32c3-hal)
-        run: cd esp32c3-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32c6-hal)
-        run: cd esp32c6-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32h2-hal)
-        run: cd esp32h2-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32p4-hal)
-        run: cd esp32p4-hal && cargo clippy -- -D warnings
 
   clippy-xtensa:
     runs-on: ubuntu-latest

esp-hal/src/analog/adc/riscv.rs

@@ -1,7 +1,10 @@
 use core::marker::PhantomData;
 
+#[cfg(not(esp32h2))]
 pub use self::calibration::*;
-use super::{AdcCalEfuse, AdcCalScheme, AdcCalSource, AdcChannel, Attenuation};
+#[cfg(not(esp32h2))]
+use super::AdcCalEfuse;
+use super::{AdcCalScheme, AdcCalSource, AdcChannel, Attenuation};
 #[cfg(any(esp32c6, esp32h2))]
 use crate::clock::clocks_ll::regi2c_write_mask;
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
@@ -646,7 +649,7 @@ macro_rules! impl_adc_interface {
 }
 
 #[cfg(esp32c2)]
-mod implementation {
+mod adc_implementation {
     use crate::peripherals::ADC1;
 
     impl_adc_interface! {
@@ -661,7 +664,7 @@ mod implementation {
 }
 
 #[cfg(esp32c3)]
-mod implementation {
+mod adc_implementation {
     use crate::peripherals::{ADC1, ADC2};
 
     impl_adc_interface! {
@@ -682,7 +685,7 @@ mod implementation {
 }
 
 #[cfg(esp32c6)]
-mod implementation {
+mod adc_implementation {
     use crate::peripherals::ADC1;
 
     impl_adc_interface! {
@@ -699,7 +702,7 @@ mod implementation {
 }
 
 #[cfg(esp32h2)]
-mod implementation {
+mod adc_implementation {
     use crate::peripherals::ADC1;
 
     impl_adc_interface! {

esp-hal/src/clock/clocks_ll/esp32h2.rs

@@ -65,7 +65,7 @@ const REGI2C_RTC_WR_CNTL_S: u8 = 24;
 const REGI2C_RTC_DATA_V: u8 = 0xFF;
 const REGI2C_RTC_DATA_S: u8 = 16;
 
-const I2C_MST_I2C0_CTRL_REG: u32 = DR_REG_I2C_ANA_MST_BASE + 0x0;
+const I2C_MST_I2C0_CTRL_REG: u32 = DR_REG_I2C_ANA_MST_BASE;
 const REGI2C_RTC_BUSY: u32 = 1 << 25;
 
 pub(crate) fn esp32h2_rtc_bbpll_configure(_xtal_freq: XtalClock, _pll_freq: PllClock) {
@@ -250,7 +250,7 @@ fn regi2c_enable_block(block: u8) {
     unsafe {
         (I2C_MST_ANA_CONF2_REG as *mut u32).write_volatile(
             // (1 << 18)
-            (I2C_MST_ANA_CONF2_REG as *mut u32).read_volatile() & !(I2C_MST_ANA_CONF2 as u32),
+            (I2C_MST_ANA_CONF2_REG as *mut u32).read_volatile() & !I2C_MST_ANA_CONF2,
         );
     }
 
@@ -339,8 +339,7 @@ pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, l
     );
     // Write the i2c bus register
     temp &= (!(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1));
-    temp =
-        ((data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32)) | temp;
+    temp |= (data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32);
     temp = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32)
         | ((reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32)
         | ((0x1 & REGI2C_RTC_WR_CNTL_V as u32) << REGI2C_RTC_WR_CNTL_S as u32)

esp-hal/src/ecc.rs

@@ -771,21 +771,21 @@ impl<'d> Ecc<'d> {
 
         let mut tmp = [0_u8; 32];
 
-        tmp[0..px.len()].copy_from_slice(&px);
+        tmp[0..px.len()].copy_from_slice(px);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8);
-        tmp[0..py.len()].copy_from_slice(&py);
+            .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &tmp, 8);
+        tmp[0..py.len()].copy_from_slice(py);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8);
-        tmp[0..qx.len()].copy_from_slice(&qx);
+            .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &tmp, 8);
+        tmp[0..qx.len()].copy_from_slice(qx);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.qx_mem(0).as_ptr(), &mut tmp, 8);
-        tmp[0..qy.len()].copy_from_slice(&qy);
+            .volatile_write_regset(self.ecc.qx_mem(0).as_ptr(), &tmp, 8);
+        tmp[0..qy.len()].copy_from_slice(qy);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.qy_mem(0).as_ptr(), &mut tmp, 8);
-        tmp[0..qz.len()].copy_from_slice(&qz);
+            .volatile_write_regset(self.ecc.qy_mem(0).as_ptr(), &tmp, 8);
+        tmp[0..qz.len()].copy_from_slice(qz);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.qz_mem(0).as_ptr(), &mut tmp, 8);
+            .volatile_write_regset(self.ecc.qz_mem(0).as_ptr(), &tmp, 8);
 
         self.ecc.mult_conf().write(|w| unsafe {
             w.work_mode()
@@ -863,12 +863,12 @@ impl<'d> Ecc<'d> {
         };
 
         let mut tmp = [0_u8; 32];
-        tmp[0..a.len()].copy_from_slice(&a);
+        tmp[0..a.len()].copy_from_slice(a);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8);
-        tmp[0..b.len()].copy_from_slice(&b);
+            .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &tmp, 8);
+        tmp[0..b.len()].copy_from_slice(b);
         self.alignment_helper
-            .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8);
+            .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &tmp, 8);
 
         self.ecc.mult_conf().write(|w| unsafe {
             w.work_mode()

esp-hal/src/gpio.rs

@@ -160,13 +160,16 @@ pub enum RtcFunction {
 pub trait RTCPin: Pin {
     #[cfg(xtensa)]
     fn rtc_number(&self) -> u8;
+
     #[cfg(any(xtensa, esp32c6))]
     fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: RtcFunction);
 
     fn rtcio_pad_hold(&mut self, enable: bool);
 
-    // Unsafe because `level` needs to be a valid setting for the
-    // rtc_cntl.gpio_wakeup.gpio_pinX_int_type
+    /// # Safety
+    ///
+    /// The `level` argument needs to be a valid setting for the
+    /// `rtc_cntl.gpio_wakeup.gpio_pinX_int_type`.
     #[cfg(any(esp32c3, esp32c6))]
     unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8);
 }
@@ -819,7 +822,7 @@ where
         unsafe {
             // there is no NMI_ENABLE but P4 could trigger 4 interrupts
             // we'll only support GPIO_INT0 for now
-            (&*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| {
+            (*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| {
                 w.int_ena()
                     .bits(gpio_intr_enable(int_enable, nmi_enable))
                     .int_type()

esp-hal/src/rtc_cntl/rtc/esp32h2.rs

@@ -326,15 +326,9 @@ impl RtcClock {
                 .modify(|_, w| w.slow_clk_sel().bits(slow_freq as u8));
             lp_clkrst.clk_to_hp().modify(|_, w| {
                 w.icg_hp_xtal32k()
-                    .bit(match slow_freq {
-                        RtcSlowClock::RtcSlowClock32kXtal => true,
-                        _ => false,
-                    })
+                    .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal))
                     .icg_hp_xtal32k()
-                    .bit(match slow_freq {
-                        RtcSlowClock::RtcSlowClock32kXtal => true,
-                        _ => false,
-                    })
+                    .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal))
             });
         }
     }

esp-hal/src/soc/esp32h2/gpio.rs

@@ -66,7 +66,7 @@ pub const ZERO_INPUT: u8 = 0x1f;
 pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
 
 pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
-    unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
+    unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
 }
 
 pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {

esp-hal/src/soc/esp32h2/mod.rs

@@ -18,6 +18,7 @@ pub mod gpio;
 pub mod peripherals;
 pub mod radio_clocks;
 
+#[allow(unused)]
 pub(crate) mod registers {
     pub const INTERRUPT_MAP_BASE: u32 = 0x60010000;
 }

esp-hal/src/soc/esp32h2/radio_clocks.rs

@@ -58,7 +58,6 @@ fn disable_phy() {
 }
 
 fn ble_ieee802154_clock_enable() {
-    let modem_lpcon = unsafe { &*esp32h2::MODEM_LPCON::PTR };
     let modem_syscon = unsafe { &*esp32h2::MODEM_SYSCON::PTR };
 
     modem_syscon
@@ -82,7 +81,7 @@ fn ble_ieee802154_clock_enable() {
             .set_bit()
     });
 
-    modem_lpcon
+    unsafe { &*esp32h2::MODEM_LPCON::PTR }
         .clk_conf()
         .modify(|_, w| w.clk_coex_en().set_bit());
 }
@@ -138,7 +137,7 @@ fn init_clocks() {
             .as_ptr()
             .write_volatile(pmu.imm_sleep_sysclk().as_ptr().read_volatile() | 1 << 28);
 
-        (&*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| {
+        (*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| {
             w.clk_i2c_mst_en()
                 .set_bit()
                 .clk_coex_en()