Rename Spi enums (#2828)

* feat: Rename Spi enums

* docs: Update changelog

* feat: Rename crate::Mode to crate::DriverMode

* docs: Udpate changelog

* feat: Rename DM type parameter to Dm for ECC

* style: rustfmt

* feat: Rename crate::Mode to crate::DriverMode

esp-hal/CHANGELOG.md

@@ -66,7 +66,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - The `PeripheralInput` and `PeripheralOutput` traits are now sealed (#2690)
 - `esp_hal::sync::Lock` has been renamed to RawMutex (#2684)
 - Updated `esp-pacs` with support for Wi-Fi on the ESP32 and made the peripheral non virtual
-
+- `SpiBitOrder`, `SpiDataMode`, `SpiMode` were renamed to `BitOder`, `DataMode` and `Mode` (#2828)
+- `crate::Mode` was renamed to `crate::DriverMode` (#2828)
 ### Fixed
 
 - Xtensa devices now correctly enable the `esp-hal-procmacros/rtc-slow` feature (#2594)

esp-hal/src/dma/gdma.rs

@@ -581,7 +581,7 @@ impl InterruptAccess<DmaRxInterrupt> for AnyGdmaRxChannel {
     }
 }
 
-impl<CH: DmaChannel, Dm: Mode> Channel<'_, Dm, CH> {
+impl<CH: DmaChannel, Dm: DriverMode> Channel<'_, Dm, CH> {
     /// Asserts that the channel is compatible with the given peripheral.
     pub fn runtime_ensure_compatible<P: DmaEligible>(&self, _peripheral: &PeripheralRef<'_, P>) {
         // No runtime checks; GDMA channels are compatible with any peripheral

esp-hal/src/dma/m2m.rs

@@ -20,7 +20,7 @@ use crate::{
     peripheral::Peripheral,
     Async,
     Blocking,
-    Mode,
+    DriverMode,
 };
 
 /// DMA Memory to Memory pseudo-Peripheral
@@ -30,7 +30,7 @@ use crate::{
 /// to memory transfers.
 pub struct Mem2Mem<'d, Dm>
 where
-    Dm: Mode,
+    Dm: DriverMode,
 {
     channel: Channel<'d, Dm, AnyGdmaChannel>,
     rx_chain: DescriptorChain,
@@ -125,7 +125,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
 
 impl<Dm> Mem2Mem<'_, Dm>
 where
-    Dm: Mode,
+    Dm: DriverMode,
 {
     /// Start a memory to memory transfer.
     pub fn start_transfer<'t, TXBUF, RXBUF>(
@@ -158,7 +158,7 @@ where
 
 impl<Dm> DmaSupport for Mem2Mem<'_, Dm>
 where
-    Dm: Mode,
+    Dm: DriverMode,
 {
     fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         while !self.channel.rx.is_done() {}
@@ -171,7 +171,7 @@ where
 
 impl<'d, Dm> DmaSupportRx for Mem2Mem<'d, Dm>
 where
-    Dm: Mode,
+    Dm: DriverMode,
 {
     type RX = ChannelRx<'d, Dm, AnyGdmaRxChannel>;
 

esp-hal/src/dma/mod.rs

@@ -18,7 +18,7 @@
 //! ```rust, no_run
 #![doc = crate::before_snippet!()]
 //! # use esp_hal::dma_buffers;
-//! # use esp_hal::spi::{master::{Config, Spi}, SpiMode};
+//! # use esp_hal::spi::{master::{Config, Spi}, Mode};
 #![cfg_attr(pdma, doc = "let dma_channel = peripherals.DMA_SPI2;")]
 #![cfg_attr(gdma, doc = "let dma_channel = peripherals.DMA_CH0;")]
 //! let sclk = peripherals.GPIO0;
@@ -28,7 +28,7 @@
 //!
 //! let mut spi = Spi::new(
 //!     peripherals.SPI2,
-//!     Config::default().with_frequency(100.kHz()).with_mode(SpiMode::Mode0)
+//!     Config::default().with_frequency(100.kHz()).with_mode(Mode::Mode0)
 //! )
 //! .unwrap()
 //! .with_sck(sclk)
@@ -69,7 +69,7 @@ use crate::{
     Async,
     Blocking,
     Cpu,
-    Mode,
+    DriverMode,
 };
 
 trait Word: crate::private::Sealed {}
@@ -1810,7 +1810,7 @@ fn create_guard(_ch: &impl RegisterAccess) -> PeripheralGuard {
 #[doc(hidden)]
 pub struct ChannelRx<'a, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaRxChannel,
 {
     pub(crate) rx_impl: PeripheralRef<'a, CH>,
@@ -1894,7 +1894,7 @@ where
 
 impl<Dm, CH> ChannelRx<'_, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaRxChannel,
 {
     /// Configure the channel.
@@ -1938,14 +1938,14 @@ where
 
 impl<Dm, CH> crate::private::Sealed for ChannelRx<'_, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaRxChannel,
 {
 }
 
 impl<Dm, CH> Rx for ChannelRx<'_, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaRxChannel,
 {
     // TODO: used by I2S, which should be rewritten to use the Preparation-based
@@ -2110,7 +2110,7 @@ pub trait Tx: crate::private::Sealed {
 #[doc(hidden)]
 pub struct ChannelTx<'a, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaTxChannel,
 {
     pub(crate) tx_impl: PeripheralRef<'a, CH>,
@@ -2188,7 +2188,7 @@ where
 
 impl<Dm, CH> ChannelTx<'_, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaTxChannel,
 {
     /// Configure the channel priority.
@@ -2232,14 +2232,14 @@ where
 
 impl<Dm, CH> crate::private::Sealed for ChannelTx<'_, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaTxChannel,
 {
 }
 
 impl<Dm, CH> Tx for ChannelTx<'_, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaTxChannel,
 {
     // TODO: used by I2S, which should be rewritten to use the Preparation-based
@@ -2450,7 +2450,7 @@ pub trait InterruptAccess<T: EnumSetType>: crate::private::Sealed {
 #[non_exhaustive]
 pub struct Channel<'d, Dm, CH>
 where
-    Dm: Mode,
+    Dm: DriverMode,
     CH: DmaChannel,
 {
     /// RX half of the channel

esp-hal/src/dma/pdma/mod.rs

@@ -197,7 +197,7 @@ pub(super) fn init_dma(_cs: CriticalSection<'_>) {
 impl<CH, Dm> Channel<'_, Dm, CH>
 where
     CH: DmaChannel,
-    Dm: Mode,
+    Dm: DriverMode,
 {
     /// Asserts that the channel is compatible with the given peripheral.
     pub fn runtime_ensure_compatible(&self, peripheral: &PeripheralRef<'_, impl DmaEligible>) {

esp-hal/src/ecc.rs

@@ -36,10 +36,10 @@ use crate::{
 };
 
 /// The ECC Accelerator driver instance
-pub struct Ecc<'d, DM: crate::Mode> {
+pub struct Ecc<'d, Dm: crate::DriverMode> {
     ecc: PeripheralRef<'d, ECC>,
     alignment_helper: AlignmentHelper<SocDependentEndianess>,
-    phantom: PhantomData<DM>,
+    phantom: PhantomData<Dm>,
     _guard: GenericPeripheralGuard<{ system::Peripheral::Ecc as u8 }>,
 }
 
@@ -125,7 +125,7 @@ impl InterruptConfigurable for Ecc<'_, crate::Blocking> {
     }
 }
 
-impl<DM: crate::Mode> Ecc<'_, DM> {
+impl<Dm: crate::DriverMode> Ecc<'_, Dm> {
     /// Resets the ECC peripheral.
     pub fn reset(&mut self) {
         self.ecc.mult_conf().reset()

esp-hal/src/i2c/master/mod.rs

@@ -64,7 +64,7 @@ use crate::{
     Async,
     Blocking,
     Cpu,
-    Mode,
+    DriverMode,
 };
 
 cfg_if::cfg_if! {
@@ -274,7 +274,7 @@ impl Default for Config {
 }
 
 /// I2C driver
-pub struct I2c<'d, Dm: Mode, T = AnyI2c> {
+pub struct I2c<'d, Dm: DriverMode, T = AnyI2c> {
     i2c: PeripheralRef<'d, T>,
     phantom: PhantomData<Dm>,
     config: Config,
@@ -283,7 +283,7 @@ pub struct I2c<'d, Dm: Mode, T = AnyI2c> {
 
 #[cfg(any(doc, feature = "unstable"))]
 #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))]
-impl<T: Instance, Dm: Mode> SetConfig for I2c<'_, Dm, T> {
+impl<T: Instance, Dm: DriverMode> SetConfig for I2c<'_, Dm, T> {
     type Config = Config;
     type ConfigError = ConfigError;
 
@@ -292,11 +292,11 @@ impl<T: Instance, Dm: Mode> SetConfig for I2c<'_, Dm, T> {
     }
 }
 
-impl<T, Dm: Mode> embedded_hal::i2c::ErrorType for I2c<'_, Dm, T> {
+impl<T, Dm: DriverMode> embedded_hal::i2c::ErrorType for I2c<'_, Dm, T> {
     type Error = Error;
 }
 
-impl<T, Dm: Mode> embedded_hal::i2c::I2c for I2c<'_, Dm, T>
+impl<T, Dm: DriverMode> embedded_hal::i2c::I2c for I2c<'_, Dm, T>
 where
     T: Instance,
 {
@@ -310,7 +310,7 @@ where
     }
 }
 
-impl<'d, T, Dm: Mode> I2c<'d, Dm, T>
+impl<'d, T, Dm: DriverMode> I2c<'d, Dm, T>
 where
     T: Instance,
 {