fix: Fix traits imports after rebase. Use debug

hil-test/.cargo/config.toml

@@ -1,12 +1,12 @@
 [alias]
-# esp32   = "test --release --features=esp32   --target=xtensa-esp32-none-elf -- --chip esp32-3.3v"
-# esp32c2 = "test --release --features=esp32c2 --target=riscv32imc-unknown-none-elf -- --chip esp32c2"
-esp32c3 = "test --release --features=esp32c3 --target=riscv32imc-unknown-none-elf -- --chip esp32c3"
-esp32c6 = "test --release --features=esp32c6 --target=riscv32imac-unknown-none-elf -- --chip esp32c6"
-esp32h2 = "test --release --features=esp32h2 --target=riscv32imac-unknown-none-elf -- --chip esp32h2"
-# esp32p4 = "test --release --features=esp32p4 --target=riscv32imafc-unknown-none-elf -- --chip esp32p4"
-# esp32s2 = "test --release --features=esp32s2 --target=xtensa-esp32s2-none-elf -- --chip esp32s2"
-esp32s3 = "test --release --features=esp32s3 --target=xtensa-esp32s3-none-elf -- --chip esp32s3"
+# esp32   = "test --features=esp32   --target=xtensa-esp32-none-elf -- --chip esp32-3.3v"
+# esp32c2 = "test --features=esp32c2 --target=riscv32imc-unknown-none-elf -- --chip esp32c2"
+esp32c3 = "test --features=esp32c3 --target=riscv32imc-unknown-none-elf -- --chip esp32c3"
+esp32c6 = "test --features=esp32c6 --target=riscv32imac-unknown-none-elf -- --chip esp32c6"
+esp32h2 = "test --features=esp32h2 --target=riscv32imac-unknown-none-elf -- --chip esp32h2"
+# esp32p4 = "test --features=esp32p4 --target=riscv32imafc-unknown-none-elf -- --chip esp32p4"
+# esp32s2 = "test --features=esp32s2 --target=xtensa-esp32s2-none-elf -- --chip esp32s2"
+esp32s3 = "test --features=esp32s3 --target=xtensa-esp32s3-none-elf -- --chip esp32s3"
 
 [target.'cfg(target_arch = "riscv32")']
 runner    = "probe-rs run"

hil-test/Cargo.toml

@@ -23,7 +23,7 @@ harness = false
 [dependencies]
 defmt = { version = "0.3.5" }
 defmt-rtt = { version = "0.4.0" }
-esp-hal = { path = "../esp-hal", features = ["embedded-hal", "defmt"], optional = true }
+esp-hal = { path = "../esp-hal", features = ["embedded-hal", "embedded-hal-02",  "defmt"], optional = true }
 embedded-hal-02       = { version = "0.2.7", package = "embedded-hal", features = ["unproven"] }
 embedded-hal-async = { version = "1.0.0", optional = true }
 embedded-hal     = { version = "1.0.0" }

hil-test/tests/spi_full_duplex.rs

@@ -12,6 +12,7 @@
 #![no_main]
 
 use defmt_rtt as _;
+use embedded_hal::spi::SpiBus;
 use esp_hal::{
     clock::ClockControl,
     gpio::IO,
@@ -61,54 +62,52 @@ mod tests {
 
     #[test]
     fn test_symestric_transfer(mut ctx: Context) {
-        use embedded_hal_02::blocking::spi::Transfer;
-
-        let mut data = [0xde, 0xad, 0xbe, 0xef];
-        let initial_data = data;
+        let write = [0xde, 0xad, 0xbe, 0xef];
+        let mut read: [u8; 4] = [0x00u8; 4];
 
         ctx.spi
-            .transfer(&mut data)
+            .transfer(&mut read[..], &write[..])
             .expect("Symmetric transfer failed");
-        assert_eq!(initial_data, data);
+        assert_eq!(write, read);
     }
 
     #[test]
     fn test_asymestric_transfer(mut ctx: Context) {
-        use embedded_hal::spi::SpiBus;
-
         let write = [0xde, 0xad, 0xbe, 0xef];
         let mut read: [u8; 4] = [0x00; 4];
-        SpiBus::transfer(&mut ctx.spi, &mut read[0..2], &write[..])
+
+        ctx.spi
+            .transfer(&mut read[0..2], &write[..])
             .expect("Asymmetric transfer failed");
         assert_eq!(write[0], read[0]);
         assert_eq!(read[2], 0x00u8);
     }
 
     #[test]
     fn test_symestric_transfer_huge_buffer(mut ctx: Context) {
-        use embedded_hal_02::blocking::spi::Transfer;
-
-        let mut data = [0x55u8; 4096];
-        for byte in 0..data.len() {
-            data[byte] = byte as u8;
+        let mut write = [0x55u8; 4096];
+        for byte in 0..write.len() {
+            write[byte] = byte as u8;
         }
-        let initial_data = data;
+        let mut read = [0x00u8; 4096];
 
-        ctx.spi.transfer(&mut data).expect("Huge transfer failed");
-        assert_eq!(initial_data, data);
+        ctx.spi
+            .transfer(&mut read[..], &write[..])
+            .expect("Huge transfer failed");
+        assert_eq!(write, read);
     }
 
     #[test]
     #[timeout(3)]
     fn test_symestric_transfer_huge_buffer_no_alloc(mut ctx: Context) {
-        use embedded_hal::spi::SpiBus;
-
         let mut write = [0x55u8; 4096];
         for byte in 0..write.len() {
             write[byte] = byte as u8;
         }
 
-        SpiBus::transfer_in_place(&mut ctx.spi, &mut write[..]).expect("Huge transfer failed");
+        ctx.spi
+            .transfer_in_place(&mut write[..])
+            .expect("Huge transfer failed");
         for byte in 0..write.len() {
             assert_eq!(write[byte], byte as u8);
         }

hil-test/tests/uart.rs

@@ -18,7 +18,8 @@ use esp_hal::{
     prelude::*,
     uart::{
         config::{Config, DataBits, Parity, StopBits},
-        TxRxPins, Uart,
+        TxRxPins,
+        Uart,
     },
 };
 use nb::block;