Eliminate the rt and vectored features from the esp-hal package (…

…#1380)

* Eliminate the `vectored` feature

* Eliminate the `rt` feature

* Update `CHANGELOG.md`

* Fix typo in comment

.github/workflows/ci.yml

@@ -91,13 +91,11 @@ jobs:
 
       # Make sure we're able to build the HAL without the default features
       # enabled:
-      # TODO: Remove `rt` and `vectored` features when able!
-      #       See: https://github.com/esp-rs/esp-hal/issues/1371
       - name: Build (no features)
         run: |
           cargo xtask build-package \
             --no-default-features \
-            --features=${{ matrix.device.soc }},rt,vectored \
+            --features=${{ matrix.device.soc }} \
             --target=${{ matrix.device.target }} \
             esp-hal
       # Build all supported examples for the specified device:

esp-hal/CHANGELOG.md

@@ -52,6 +52,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Remove package-level type exports (#1275)
 - Removed `direct-vectoring` & `interrupt-preemption` features, as they are now enabled by default (#1310)
+- Removed the `rt` and `vectored` features (#1380)
 
 ## [0.16.1] - 2024-03-12
 

esp-hal/Cargo.toml

@@ -40,7 +40,7 @@ log                  = { version = "0.4.21", optional = true }
 nb                   = "1.1.0"
 paste                = "1.0.14"
 portable-atomic      = { version = "1.6.0", default-features = false }
-procmacros           = { version = "0.9.0", features = ["enum-dispatch", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
+procmacros           = { version = "0.9.0", features = ["enum-dispatch", "interrupt", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
 riscv                = { version = "0.11.1", optional = true }
 strum                = { version = "0.26.1", default-features = false, features = ["derive"] }
 void                 = { version = "1.0.2", default-features = false }
@@ -52,20 +52,20 @@ xtensa-lx            = { version = "0.9.0", optional = true }
 # IMPORTANT:
 # Each supported device MUST have its PAC included below along with a
 # corresponding feature.
-esp32   = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
-esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section"], optional = true }
+esp32   = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
+esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "a8a8340", features = ["critical-section", "rt"], optional = true }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
-esp-riscv-rt = { version = "0.7.0", optional = true, path = "../esp-riscv-rt" }
+esp-riscv-rt = { version = "0.7.0", path = "../esp-riscv-rt" }
 
 [target.'cfg(target_arch = "xtensa")'.dependencies]
-xtensa-lx-rt = { version = "0.16.0", optional = true }
+xtensa-lx-rt = "0.16.0"
 
 [build-dependencies]
 basic-toml   = "0.1.8"
@@ -75,9 +75,9 @@ esp-metadata = { version = "0.1.0", path = "../esp-metadata" }
 serde        = { version = "1.0.197", features = ["derive"] }
 
 [features]
-default = ["embedded-hal", "rt", "vectored"]
+default = ["embedded-hal"]
 
-riscv  = ["dep:riscv",     "critical-section/restore-state-u8",  "esp-riscv-rt?/zero-bss"]
+riscv  = ["dep:riscv",     "critical-section/restore-state-u8",  "esp-riscv-rt/zero-bss"]
 xtensa = ["dep:xtensa-lx", "critical-section/restore-state-u32"]
 
 bluetooth = []
@@ -97,27 +97,12 @@ debug = [
 ]
 ## Enable logging output using the `log` crate.
 log = ["dep:log"]
-## Enable runtime support.
-rt = [
-    "dep:esp-riscv-rt",
-    "dep:xtensa-lx-rt",
-    "esp32?/rt",
-    "esp32c2?/rt",
-    "esp32c3?/rt",
-    "esp32c6?/rt",
-    "esp32h2?/rt",
-    "esp32p4?/rt",
-    "esp32s2?/rt",
-    "esp32s3?/rt",
-]
-## Enable interrupt vectoring.
-vectored = ["procmacros/interrupt"]
 ## Configuration for placing device drivers in the IRAM for faster access.
 place-spi-driver-in-ram = []
 
 # Chip Support Feature Flags
 # Target the ESP32.
-esp32   = ["dep:esp32",   "xtensa", "xtensa-lx/spin", "xtensa-lx-rt?/esp32"]
+esp32   = ["dep:esp32",   "xtensa", "xtensa-lx/spin", "xtensa-lx-rt/esp32"]
 # Target the ESP32-C2.
 esp32c2 = ["dep:esp32c2", "riscv",  "portable-atomic/unsafe-assume-single-core"]
 # Target the ESP32-C3.
@@ -129,20 +114,20 @@ esp32h2 = ["dep:esp32h2", "riscv", "rv-zero-rtc-bss"]
 # Target the ESP32-P4.
 esp32p4 = ["dep:esp32p4", "riscv",  "procmacros/has-lp-core", "rv-zero-rtc-bss"]
 # Target the ESP32-S2.
-esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt?/esp32s2", "usb-otg"]
+esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
 # Target the ESP32-S3.
-esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx/spin", "xtensa-lx-rt?/esp32s3", "usb-otg"]
+esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx/spin", "xtensa-lx-rt/esp32s3", "usb-otg"]
 
 #! ### RISC-V Exclusive Feature Flags
 ## Move the stack to start of RAM to get zero-cost stack overflow protection
 ## (ESP32-C6 and ESPS32-H2 only!).
 flip-link = ["esp-riscv-rt/fix-sp"]
 ## Initialize the `.data` section of memory.
-rv-init-data = ["esp-riscv-rt?/init-data", "esp-riscv-rt?/init-rw-text"]
+rv-init-data = ["esp-riscv-rt/init-data", "esp-riscv-rt/init-rw-text"]
 ## Zero the `.bss` section of low-power memory.
-rv-zero-rtc-bss = ["esp-riscv-rt?/zero-rtc-fast-bss"]
+rv-zero-rtc-bss = ["esp-riscv-rt/zero-rtc-fast-bss"]
 ## Initialize the `.data` section of low-power memory.
-rv-init-rtc-data = ["esp-riscv-rt?/init-rtc-fast-data", "esp-riscv-rt?/init-rtc-fast-text"]
+rv-init-rtc-data = ["esp-riscv-rt/init-rtc-fast-data", "esp-riscv-rt/init-rtc-fast-text"]
 
 #! ### Trait Implementation Feature Flags
 ## Enable support for asynchronous operation, with interfaces provided by

esp-hal/src/dma/gdma.rs

@@ -394,7 +394,6 @@ macro_rules! impl_channel {
             pub type [<Channel $num InterruptBinder>] = ChannelInterruptBinder<$num>;
 
             impl InterruptBinder for ChannelInterruptBinder<$num> {
-                #[cfg(feature = "vectored")]
                 fn set_isr(handler: $crate::interrupt::InterruptHandler) {
                     let mut dma = unsafe { crate::peripherals::DMA::steal() };
                     $(

esp-hal/src/dma/mod.rs

@@ -1298,7 +1298,6 @@ pub trait ChannelTypes {
 }
 
 pub trait InterruptBinder {
-    #[cfg(feature = "vectored")]
     fn set_isr(handler: InterruptHandler);
 }
 
@@ -1321,7 +1320,6 @@ where
     /// with [crate::interrupt::Priority::max()]
     ///
     /// Interrupts are not enabled at the peripheral level here.
-    #[cfg(feature = "vectored")]
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
         C::Binder::set_isr(handler);
     }

esp-hal/src/dma/pdma.rs

@@ -26,7 +26,6 @@ macro_rules! ImplSpiChannel {
             pub struct [<Channel $num InterruptBinder>] {}
 
             impl InterruptBinder for [<Channel $num InterruptBinder>] {
-                #[cfg(feature = "vectored")]
                 fn set_isr(handler: $crate::interrupt::InterruptHandler) {
                     let mut spi = unsafe { $crate::peripherals::[< SPI $num >]::steal() };
                     spi.[< bind_spi $num _dma_interrupt>](handler.handler());
@@ -376,7 +375,6 @@ macro_rules! ImplI2sChannel {
             pub struct [<Channel $num InterruptBinder>] {}
 
             impl InterruptBinder for [<Channel $num InterruptBinder>] {
-                #[cfg(feature = "vectored")]
                 fn set_isr(handler:  $crate::interrupt::InterruptHandler) {
                     let mut i2s = unsafe { $crate::peripherals::[< I2S $num >]::steal() };
                     i2s.[< bind_i2s $num _interrupt>](handler.handler());

esp-hal/src/interrupt/mod.rs

@@ -2,19 +2,18 @@
 //!
 //! Interrupt support functionality depends heavily on the features enabled.
 //!
-//! When the `vectored` feature is enabled, the
-//! [`enable`] method will map interrupt to a CPU
-//! interrupt, and handle the `vector`ing to the peripheral interrupt, for
-//! example `UART0`.
+//! The [`enable`] method will map interrupt to a CPU interrupt, and handle the
+//! vectoring to the peripheral interrupt, for example `UART0`.
 //!
 //! It is also possible, but not recommended, to bind an interrupt directly to a
 //! CPU interrupt. This can offer lower latency, at the cost of more complexity
 //! in the interrupt handler.
 //!
-//! The `vectored` reserves a number of CPU interrupts, which cannot be used see
+//! We reserve a number of CPU interrupts, which cannot be used; see
 //! [`RESERVED_INTERRUPTS`].
 //!
 //! ## Example
+//!
 //! ```no_run
 //! #[entry]
 //! fn main() -> ! {

esp-hal/src/interrupt/riscv.rs

@@ -1,7 +1,7 @@
 //! Interrupt handling - RISC-V
 //!
-//! When the `vectored` feature is enabled, CPU interrupts 1 through 15 are
-//! reserved for each of the possible interrupt priorities.
+//! CPU interrupts 1 through 15 are reserved for each of the possible interrupt
+//! priorities.
 //!
 //! On chips with a PLIC CPU interrupts 1,2,5,6,9 .. 19 are used.
 //!
@@ -24,6 +24,7 @@ pub use self::classic::*;
 pub use self::clic::*;
 #[cfg(plic)]
 pub use self::plic::*;
+pub use self::vectored::*;
 use crate::{
     peripherals::{self, Interrupt},
     Cpu,
@@ -34,7 +35,6 @@ use crate::{
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     InvalidInterruptPriority,
-    #[cfg(feature = "vectored")]
     CpuInterruptReserved,
 }
 
@@ -134,10 +134,6 @@ impl Priority {
     }
 }
 
-#[cfg(feature = "vectored")]
-pub use vectored::*;
-
-#[cfg(feature = "vectored")]
 pub const RESERVED_INTERRUPTS: &[usize] = INTERRUPT_TO_PRIORITY;
 
 /// # Safety
@@ -181,7 +177,6 @@ pub fn _setup_interrupts() {
         let vec_table = &_vector_table as *const _ as usize;
         mtvec::write(vec_table, mtvec::TrapMode::Vectored);
 
-        #[cfg(feature = "vectored")]
         crate::interrupt::init_vectoring();
     };
 
@@ -193,17 +188,15 @@ pub fn _setup_interrupts() {
 
 /// Enable an interrupt by directly binding it to a available CPU interrupt
 ///
-/// Unless you are sure, you most likely want to use [`enable`] with the
-/// `vectored` feature enabled instead.
+/// Unless you are sure, you most likely want to use [`enable`] instead.
 ///
-/// When the `vectored` feature is enabled, trying using a reserved interrupt
-/// from [`RESERVED_INTERRUPTS`] will return an error.
+/// Trying using a reserved interrupt from [`RESERVED_INTERRUPTS`] will return
+/// an error.
 pub fn enable_direct(
     interrupt: Interrupt,
     level: Priority,
     cpu_interrupt: CpuInterrupt,
 ) -> Result<(), Error> {
-    #[cfg(feature = "vectored")]
     if RESERVED_INTERRUPTS.contains(&(cpu_interrupt as _)) {
         return Err(Error::CpuInterruptReserved);
     }
@@ -292,9 +285,7 @@ pub fn get_status(_core: Cpu) -> u128 {
 
 /// Assign a peripheral interrupt to an CPU interrupt.
 ///
-/// Great care must be taken when using the `vectored` feature,
-/// do not use CPU interrupts in the [`RESERVED_INTERRUPTS`] when
-/// the `vectored` feature is enabled.
+/// Do not use CPU interrupts in the [`RESERVED_INTERRUPTS`].
 pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) {
     let interrupt_number = interrupt as isize;
     let cpu_interrupt_number = which as isize;
@@ -325,7 +316,6 @@ unsafe fn get_assigned_cpu_interrupt(interrupt: Interrupt) -> Option<CpuInterrup
     }
 }
 
-#[cfg(feature = "vectored")]
 mod vectored {
     use procmacros::ram;
 
@@ -582,8 +572,7 @@ mod classic {
 
     /// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
     ///
-    /// This is safe to call when the `vectored` feature is enabled. The
-    /// vectored interrupt handler will take care of clearing edge interrupt
+    /// The vectored interrupt handler will take care of clearing edge interrupt
     /// bits.
     pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
         unsafe {
@@ -605,9 +594,8 @@ mod classic {
 
     /// Set the priority level of an CPU interrupt
     ///
-    /// Great care must be taken when using the `vectored` feature (enabled by
-    /// default). Avoid changing the priority of interrupts 1 - 15 when
-    /// interrupt vectoring is enabled.
+    /// Great care must be taken when using this function; avoid changing the
+    /// priority of interrupts 1 - 15.
     pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
         let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
         let cpu_interrupt_number = which as isize;
@@ -714,8 +702,7 @@ mod plic {
 
     /// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
     ///
-    /// This is safe to call when the `vectored` feature is enabled. The
-    /// vectored interrupt handler will take care of clearing edge interrupt
+    /// The vectored interrupt handler will take care of clearing edge interrupt
     /// bits.
     pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
         unsafe {
@@ -735,9 +722,8 @@ mod plic {
 
     /// Set the priority level of an CPU interrupt
     ///
-    /// Great care must be taken when using the `vectored` feature (enabled by
-    /// default). Avoid changing the priority of interrupts 1 - 15 when
-    /// interrupt vectoring is enabled.
+    /// Great care must be taken when using this function; avoid changing the
+    /// priority of interrupts 1 - 15.
     pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
         let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
 
@@ -870,8 +856,7 @@ mod clic {
 
     /// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
     ///
-    /// This is safe to call when the `vectored` feature is enabled. The
-    /// vectored interrupt handler will take care of clearing edge interrupt
+    /// The vectored interrupt handler will take care of clearing edge interrupt
     /// bits.
     pub fn set_kind(core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
         let cpu_interrupt_number = which as usize;
@@ -888,9 +873,8 @@ mod clic {
 
     /// Set the priority level of an CPU interrupt
     ///
-    /// Great care must be taken when using the `vectored` feature (enabled by
-    /// default). Avoid changing the priority of interrupts 1 - 15 when
-    /// interrupt vectoring is enabled.
+    /// Great care must be taken when using this function; avoid changing the
+    /// priority of interrupts 1 - 15.
     pub unsafe fn set_priority(core: Cpu, which: CpuInterrupt, priority: Priority) {
         let cpu_interrupt_number = which as usize;
         let intr_cntrl = intr_cntrl(core, cpu_interrupt_number);