Unify the low-power peripheral names (RTC_CNTL and LP_CLKRST to `…

…LPWR`) (#1064) * WIP * Adjusting to changes in driver * Adding CHANGELOG entry
esp-rs · Jan 8, 2024 · fdc1dbf · fdc1dbf
1 parent cf66cc0
commit fdc1dbf
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -24,6 +24,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Removed
 
+### Breaking
+- Unify the low-power peripheral names (`RTC_CNTL` and `LP_CLKRST` to `LPWR`) (#1064)
+
 ## [0.14.1] - 2023-12-13
 
 ### Fixed

diff --git a/esp-hal-common/src/gpio.rs b/esp-hal-common/src/gpio.rs
@@ -1691,7 +1691,7 @@ macro_rules! rtc_pins {
             }
 
             fn rtcio_pad_hold(&mut self, enable: bool) {
-                let rtc_ctrl = unsafe { &*crate::peripherals::RTC_CNTL::PTR };
+                let rtc_ctrl = unsafe { &*crate::peripherals::LPWR::PTR };
 
                 #[cfg(esp32)]
                 rtc_ctrl.hold_force().modify(|_, w| w.$hold().bit(enable));

diff --git a/esp-hal-common/src/otg_fs.rs b/esp-hal-common/src/otg_fs.rs
@@ -110,7 +110,7 @@ where
 
             #[cfg(esp32s3)]
             {
-                let rtc = &*peripherals::RTC_CNTL::PTR;
+                let rtc = &*peripherals::LPWR::PTR;
                 rtc.usb_conf()
                     .modify(|_, w| w.sw_hw_usb_phy_sel().set_bit().sw_usb_phy_sel().set_bit());
             }

diff --git a/esp-hal-common/src/peripheral.rs b/esp-hal-common/src/peripheral.rs
@@ -29,7 +29,7 @@
 //! ```
 //! ### Accessing peripherals
 //! ```no_run
-//! let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+//! let mut rtc = Rtc::new(peripherals.LPWR);
 //! ```
 //! ```no_run
 //! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);

diff --git a/esp-hal-common/src/rtc_cntl/mod.rs b/esp-hal-common/src/rtc_cntl/mod.rs
@@ -79,10 +79,10 @@ pub use self::rtc::SocResetReason;
 use crate::clock::XtalClock;
 #[cfg(not(esp32))]
 use crate::efuse::Efuse;
+#[cfg(not(any(esp32c6, esp32h2)))]
+use crate::peripherals::{LPWR, TIMG0};
 #[cfg(any(esp32c6, esp32h2))]
 use crate::peripherals::{LP_TIMER, LP_WDT};
-#[cfg(not(any(esp32c6, esp32h2)))]
-use crate::peripherals::{RTC_CNTL, TIMG0};
 #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))]
 use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers};
 use crate::{
@@ -95,11 +95,6 @@ use crate::{
 #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))]
 pub mod sleep;
 
-#[cfg(any(esp32c6, esp32h2))]
-type RtcCntl = crate::peripherals::LP_CLKRST;
-#[cfg(not(any(esp32c6, esp32h2)))]
-type RtcCntl = crate::peripherals::RTC_CNTL;
-
 #[cfg_attr(esp32, path = "rtc/esp32.rs")]
 #[cfg_attr(esp32c2, path = "rtc/esp32c2.rs")]
 #[cfg_attr(esp32c3, path = "rtc/esp32c3.rs")]
@@ -194,14 +189,14 @@ pub(crate) enum RtcCalSel {
 
 /// Low-power Management
 pub struct Rtc<'d> {
-    _inner: PeripheralRef<'d, RtcCntl>,
+    _inner: PeripheralRef<'d, crate::peripherals::LPWR>,
     pub rwdt: Rwdt,
     #[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
     pub swd: Swd,
 }
 
 impl<'d> Rtc<'d> {
-    pub fn new(rtc_cntl: impl Peripheral<P = RtcCntl> + 'd) -> Self {
+    pub fn new(rtc_cntl: impl Peripheral<P = crate::peripherals::LPWR> + 'd) -> Self {
         rtc::init();
         rtc::configure_clock();
 
@@ -227,7 +222,7 @@ impl<'d> Rtc<'d> {
     /// read the current value of the rtc time registers.
     pub fn get_time_raw(&self) -> u64 {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::ptr() };
+        let rtc_cntl = unsafe { &*LPWR::ptr() };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_TIMER::ptr() };
 
@@ -346,7 +341,7 @@ impl RtcClock {
     /// disabled to reduce power consumption.
     #[cfg(not(any(esp32c6, esp32h2)))]
     fn enable_8m(clk_8m_en: bool, d256_en: bool) {
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
 
         if clk_8m_en {
             rtc_cntl.clk_conf().modify(|_, w| w.enb_ck8m().clear_bit());
@@ -376,7 +371,7 @@ impl RtcClock {
     /// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the
     /// bootloader, as passed to rtc_clk_init function.
     pub fn get_xtal_freq() -> XtalClock {
-        let xtal_freq_reg = unsafe { &*RTC_CNTL::PTR }.store4().read().bits();
+        let xtal_freq_reg = unsafe { &*LPWR::PTR }.store4().read().bits();
 
         // Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
         // lower and upper 16-bit halves. These are the routines to work with such a
@@ -405,7 +400,7 @@ impl RtcClock {
     /// Get the RTC_SLOW_CLK source
     #[cfg(not(any(esp32c6, esp32h2)))]
     pub fn get_slow_freq() -> RtcSlowClock {
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         let slow_freq = rtc_cntl.clk_conf().read().ana_clk_rtc_sel().bits();
         match slow_freq {
             0 => RtcSlowClock::RtcSlowClockRtc,
@@ -419,7 +414,7 @@ impl RtcClock {
     #[cfg(not(any(esp32c6, esp32h2)))]
     fn set_slow_freq(slow_freq: RtcSlowClock) {
         unsafe {
-            let rtc_cntl = &*RTC_CNTL::PTR;
+            let rtc_cntl = &*LPWR::PTR;
             rtc_cntl.clk_conf().modify(|_, w| {
                 w.ana_clk_rtc_sel()
                     .bits(slow_freq as u8)
@@ -448,7 +443,7 @@ impl RtcClock {
     #[cfg(not(any(esp32c6, esp32h2)))]
     fn set_fast_freq(fast_freq: RtcFastClock) {
         unsafe {
-            let rtc_cntl = &*RTC_CNTL::PTR;
+            let rtc_cntl = &*LPWR::PTR;
             rtc_cntl.clk_conf().modify(|_, w| {
                 w.fast_clk_rtc_sel().bit(match fast_freq {
                     RtcFastClock::RtcFastClock8m => true,
@@ -479,7 +474,7 @@ impl RtcClock {
             RtcCalSel::RtcCalInternalOsc => RtcCalSel::RtcCalRtcMux,
             _ => cal_clk,
         };
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         let timg0 = unsafe { &*TIMG0::PTR };
 
         // Enable requested clock (150k clock is always on)
@@ -656,7 +651,7 @@ impl RtcClock {
         // Number of 8M/256 clock cycles to use for XTAL frequency estimation.
         const XTAL_FREQ_EST_CYCLES: u32 = 10;
 
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         let clk_8m_enabled = rtc_cntl.clk_conf().read().enb_ck8m().bit_is_clear();
         let clk_8md256_enabled = rtc_cntl.clk_conf().read().enb_ck8m_div().bit_is_clear();
 
@@ -719,7 +714,7 @@ impl Rwdt {
 
     pub fn listen(&mut self) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -744,7 +739,7 @@ impl Rwdt {
 
     pub fn unlisten(&mut self) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -771,7 +766,7 @@ impl Rwdt {
 
     pub fn clear_interrupt(&mut self) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -787,7 +782,7 @@ impl Rwdt {
 
     pub fn is_interrupt_set(&self) -> bool {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -802,7 +797,7 @@ impl Rwdt {
 
     pub fn feed(&mut self) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -813,7 +808,7 @@ impl Rwdt {
 
     fn set_write_protection(&mut self, enable: bool) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -824,7 +819,7 @@ impl Rwdt {
 
     fn set_enabled(&mut self, enable: bool) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -839,7 +834,7 @@ impl Rwdt {
 
     fn set_timeout(&mut self, timeout: MicrosDurationU64) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -929,7 +924,7 @@ impl Swd {
     /// Enable/disable write protection for WDT registers
     fn set_write_protection(&mut self, enable: bool) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -945,7 +940,7 @@ impl Swd {
 
     fn set_enabled(&mut self, enable: bool) {
         #[cfg(not(any(esp32c6, esp32h2)))]
-        let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+        let rtc_cntl = unsafe { &*LPWR::PTR };
         #[cfg(any(esp32c6, esp32h2))]
         let rtc_cntl = unsafe { &*LP_WDT::PTR };
 
@@ -986,19 +981,15 @@ pub fn get_wakeup_cause() -> SleepSource {
     });
     #[cfg(not(any(esp32, esp32c6, esp32h2)))]
     let wakeup_cause = WakeupReason::from_bits_retain(unsafe {
-        (&*RTC_CNTL::PTR)
+        (&*LPWR::PTR)
             .slp_wakeup_cause()
             .read()
             .wakeup_cause()
             .bits()
     });
     #[cfg(esp32)]
     let wakeup_cause = WakeupReason::from_bits_retain(unsafe {
-        (&*RTC_CNTL::PTR)
-            .wakeup_state()
-            .read()
-            .wakeup_cause()
-            .bits() as u32
+        (&*LPWR::PTR).wakeup_state().read().wakeup_cause().bits() as u32
     });
 
     if wakeup_cause.contains(WakeupReason::TimerTrigEn) {

diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs
@@ -3,7 +3,7 @@ use strum::FromRepr;
 
 use crate::{
     clock::{clocks_ll::regi2c_write_mask, Clock, XtalClock},
-    peripherals::{LP_AON, LP_CLKRST, PCR, PMU, TIMG0},
+    peripherals::{LPWR, LP_AON, PCR, PMU, TIMG0},
 };
 
 const I2C_PMU: u8 = 0x6d;
@@ -306,7 +306,7 @@ impl RtcClock {
     fn set_fast_freq(fast_freq: RtcFastClock) {
         // components/hal/esp32s2/include/hal/clk_tree_ll.h
         unsafe {
-            let lp_clkrst = &*LP_CLKRST::PTR;
+            let lp_clkrst = &*LPWR::PTR;
             lp_clkrst.lp_clk_conf().modify(|_, w| {
                 w.fast_clk_sel().bits(match fast_freq {
                     RtcFastClock::RtcFastClockRcFast => 0b00,
@@ -319,7 +319,7 @@ impl RtcClock {
 
     fn set_slow_freq(slow_freq: RtcSlowClock) {
         unsafe {
-            let lp_clkrst = &*LP_CLKRST::PTR;
+            let lp_clkrst = &*LPWR::PTR;
 
             lp_clkrst
                 .lp_clk_conf()
@@ -341,7 +341,7 @@ impl RtcClock {
 
     /// Get the RTC_SLOW_CLK source
     pub(crate) fn get_slow_freq() -> RtcSlowClock {
-        let lp_clrst = unsafe { &*LP_CLKRST::ptr() };
+        let lp_clrst = unsafe { &*LPWR::ptr() };
 
         let slow_freq = lp_clrst.lp_clk_conf().read().slow_clk_sel().bits();
         match slow_freq {
@@ -382,7 +382,7 @@ impl RtcClock {
             };
         }
 
-        let lp_clkrst = unsafe { &*LP_CLKRST::ptr() };
+        let lp_clkrst = unsafe { &*LPWR::ptr() };
         let pcr = unsafe { &*PCR::ptr() };
         let pmu = unsafe { &*PMU::ptr() };
 

diff --git a/esp-hal-common/src/soc/esp32/mod.rs b/esp-hal-common/src/soc/esp32/mod.rs
@@ -5,7 +5,7 @@
 //! The `SOC` module provides access, functions and structures that are useful
 //! for interacting with various system-related peripherals on `ESP32` chip.
 
-use self::peripherals::{RTC_CNTL, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
 use crate::{timer::Wdt, Rtc};
 
 pub mod cpu_control;
@@ -74,7 +74,7 @@ pub extern "Rust" fn __init_data() -> bool {
 #[export_name = "__post_init"]
 unsafe fn post_init() {
     // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(RTC_CNTL::steal());
+    let mut rtc = Rtc::new(LPWR::steal());
     rtc.rwdt.disable();
 
     Wdt::<TIMG0>::set_wdt_enabled(false);

diff --git a/esp-hal-common/src/soc/esp32/peripherals.rs b/esp-hal-common/src/soc/esp32/peripherals.rs
@@ -51,7 +51,7 @@ crate::peripherals! {
     RMT <= RMT,
     RNG <= RNG,
     RSA <= RSA,
-    RTC_CNTL <= RTC_CNTL,
+    LPWR <= RTC_CNTL,
     RTC_IO <= RTC_IO,
     RTC_I2C <= RTC_I2C,
     SDHOST <= SDHOST,

diff --git a/esp-hal-common/src/soc/esp32c2/mod.rs b/esp-hal-common/src/soc/esp32c2/mod.rs
@@ -5,7 +5,7 @@
 //! The `SOC` module provides access, functions and structures that are useful
 //! for interacting with various system-related peripherals on `ESP32-C2` chip.
 
-use self::peripherals::{RTC_CNTL, TIMG0};
+use self::peripherals::{LPWR, TIMG0};
 use crate::{timer::Wdt, Rtc};
 
 pub mod efuse;
@@ -25,7 +25,7 @@ pub(crate) mod constants {
 #[export_name = "__post_init"]
 unsafe fn post_init() {
     // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(RTC_CNTL::steal());
+    let mut rtc = Rtc::new(LPWR::steal());
     rtc.swd.disable();
     rtc.rwdt.disable();
 

diff --git a/esp-hal-common/src/soc/esp32c2/peripherals.rs b/esp-hal-common/src/soc/esp32c2/peripherals.rs
@@ -40,8 +40,8 @@ crate::peripherals! {
     INTERRUPT_CORE0 <= INTERRUPT_CORE0,
     IO_MUX <= IO_MUX,
     LEDC <= LEDC,
+    LPWR <= RTC_CNTL,
     RNG <= RNG,
-    RTC_CNTL <= RTC_CNTL,
     SENSITIVE <= SENSITIVE,
     SHA <= SHA,
     SPI0 <= SPI0,

diff --git a/esp-hal-common/src/soc/esp32c3/mod.rs b/esp-hal-common/src/soc/esp32c3/mod.rs
@@ -9,7 +9,7 @@
 //!    * I2S_SCLK: 160_000_000 - I2S clock frequency
 //!    * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
 
-use self::peripherals::{RTC_CNTL, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
 use crate::{timer::Wdt, Rtc};
 
 pub mod efuse;
@@ -37,7 +37,7 @@ pub(crate) mod constants {
 #[export_name = "__post_init"]
 unsafe fn post_init() {
     // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(RTC_CNTL::steal());
+    let mut rtc = Rtc::new(LPWR::steal());
     rtc.swd.disable();
     rtc.rwdt.disable();
 

diff --git a/esp-hal-common/src/soc/esp32c3/peripherals.rs b/esp-hal-common/src/soc/esp32c3/peripherals.rs
@@ -44,10 +44,10 @@ crate::peripherals! {
     INTERRUPT_CORE0 <= INTERRUPT_CORE0,
     IO_MUX <= IO_MUX,
     LEDC <= LEDC,
+    LPWR <= RTC_CNTL,
     RMT <= RMT,
     RNG <= RNG,
     RSA <= RSA,
-    RTC_CNTL <= RTC_CNTL,
     SENSITIVE <= SENSITIVE,
     SHA <= SHA,
     SPI0 <= SPI0,