Move binary logging to sys crate

esp-hal/CHANGELOG.md

@@ -24,6 +24,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Added `Rtc::set_current_time` to allow setting RTC time, and `Rtc::current_time` to getting RTC time while taking into account boot time (#1883)
 - Added APIs to allow connecting signals through the GPIO matrix. (#2128)
 - Implement `TryFrom<u32>` for `ledc::timer::config::Duty` (#1984)
+- Expose `RtcClock::get_xtal_freq` and `RtcClock::get_slow_freq` publically for all chips (#2183)
 
 ### Changed
 

esp-hal/src/rtc_cntl/mod.rs

@@ -1116,3 +1116,11 @@ pub fn get_wakeup_cause() -> SleepSource {
 
     SleepSource::Undefined
 }
+
+// libphy.a can pull this in on some chips, we provide it here in the hal
+// so that either ieee or esp-wifi gets it for free without duplicating in both
+#[no_mangle]
+extern "C" fn rtc_clk_xtal_freq_get() -> i32 {
+    let xtal = RtcClock::get_xtal_freq();
+    xtal.mhz() as i32
+}

esp-hal/src/rtc_cntl/rtc/esp32c6.rs

@@ -1372,7 +1372,7 @@ impl Clock for RtcFastClock {
 #[allow(clippy::enum_variant_names)]
 #[derive(Debug, Clone, Copy, PartialEq)]
 /// RTC SLOW_CLK frequency values
-pub(crate) enum RtcSlowClock {
+pub enum RtcSlowClock {
     /// Select RC_SLOW_CLK as RTC_SLOW_CLK source
     RtcSlowClockRcSlow  = 0,
     /// Select XTAL32K_CLK as RTC_SLOW_CLK source
@@ -1426,7 +1426,7 @@ impl RtcClock {
     const CAL_FRACT: u32 = 19;
 
     // rtc_clk_xtal_freq_get
-    fn get_xtal_freq_mhz() -> u32 {
+    pub(crate) fn get_xtal_freq_mhz() -> u32 {
         let xtal_freq_reg = unsafe { lp_aon().store4().read().bits() };
 
         // Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
@@ -1447,15 +1447,15 @@ impl RtcClock {
     /// Get main XTAL frequency
     /// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the
     /// bootloader, as passed to rtc_clk_init function.
-    fn get_xtal_freq() -> XtalClock {
+    pub fn get_xtal_freq() -> XtalClock {
         match Self::get_xtal_freq_mhz() {
             40 => XtalClock::RtcXtalFreq40M,
             other => XtalClock::RtcXtalFreqOther(other),
         }
     }
 
     /// Get the RTC_SLOW_CLK source
-    pub(crate) fn get_slow_freq() -> RtcSlowClock {
+    pub fn get_slow_freq() -> RtcSlowClock {
         let lp_clrst = unsafe { lp_clkrst() };
 
         let slow_freq = lp_clrst.lp_clk_conf().read().slow_clk_sel().bits();

esp-hal/src/rtc_cntl/rtc/esp32h2.rs

@@ -215,8 +215,9 @@ impl Clock for RtcFastClock {
 
 /// RTC SLOW_CLK frequency values
 #[allow(clippy::enum_variant_names)]
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub(crate) enum RtcSlowClock {
+#[derive(Debug, Clone, Copy)]
+#[non_exhaustive]
+pub enum RtcSlowClock {
     /// Select RC_SLOW_CLK as RTC_SLOW_CLK source
     RtcSlowClockRcSlow  = 0,
     /// Select XTAL32K_CLK as RTC_SLOW_CLK source
@@ -270,8 +271,10 @@ pub struct RtcClock;
 impl RtcClock {
     const CAL_FRACT: u32 = 19;
 
-    /// Calculate the necessary RTC_SLOW_CLK cycles to complete 1 millisecond.
-    fn get_xtal_freq() -> XtalClock {
+    /// Get main XTAL frequency.
+    /// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the
+    /// bootloader, as passed to rtc_clk_init function.
+    pub fn get_xtal_freq() -> XtalClock {
         let xtal_freq_reg = unsafe { &*LP_AON::PTR }.store4().read().bits();
 
         // Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
@@ -324,7 +327,7 @@ impl RtcClock {
     }
 
     /// Get the RTC_SLOW_CLK source
-    pub(crate) fn get_slow_freq() -> RtcSlowClock {
+    pub fn get_slow_freq() -> RtcSlowClock {
         let lp_clrst = unsafe { &*LPWR::ptr() };
 
         let slow_freq = lp_clrst.lp_clk_conf().read().slow_clk_sel().bits();

esp-ieee802154/CHANGELOG.md

@@ -10,15 +10,18 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Added
 
 - Added board-specific consts for c6 and h2 when caluclating transmit power conversion
+- Added `defmt` and `log` features (#2183)
 
 ### Changed
 
-- Modified CCA threshold value to default of -60 
+- Modified CCA threshold value to default of -60
+- The driver now take `RADIO_CLK` by value to avoid a collision with esp-wifi's usage (#2183)
+- `binary-logs` feature renamed to `sys-logs` (#2183)
 
 ### Fixed
 
 - Fixed possible integer underflow in array access
-- Fixed compile error when building binary-logs feature
+- Fixed compile error when building sys-logs feature
 
 ### Removed
 

esp-ieee802154/Cargo.toml

@@ -20,17 +20,20 @@ byte              = "0.2.7"
 critical-section  = "1.1.3"
 document-features = "0.2.10"
 esp-hal           = { version = "0.20.0", path = "../esp-hal" }
-esp-wifi-sys      = "0.5.0"
+esp-wifi-sys      = { version = "0.5.0", git = "https://github.com/esp-rs/esp-wifi-sys", rev = "83ee3bd" }
 heapless          = "0.8.0"
 ieee802154        = "0.6.1"
-log               = "0.4.22"
 vcell             = "0.1.3"
 cfg-if            = "1.0.0"
 
+defmt = { version = "0.3.8", optional = true }
+log = { version = "0.4.22", optional = true }
+
 
 [features]
 esp32c6 = ["esp-hal/esp32c6", "esp-wifi-sys/esp32c6"]
 esp32h2 = ["esp-hal/esp32h2", "esp-wifi-sys/esp32h2"]
+sys-logs = ["esp-wifi-sys/sys-logs"]
 
-## Output logging from the PHY blobs. Requires nightly.
-binary-logs = []
+log = ["dep:log", "esp-wifi-sys/log"]
+defmt = ["dep:defmt", "esp-wifi-sys/defmt"]