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Update revision of PACs and fix all build errors #2515

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Nov 11, 2024
Merged

Update revision of PACs and fix all build errors #2515

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14 changes: 7 additions & 7 deletions esp-hal/Cargo.toml
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Expand Up @@ -56,13 +56,13 @@ xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
esp32 = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }
esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }
esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }
esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }
esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }
esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }
esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }
Expand Down
2 changes: 1 addition & 1 deletion esp-hal/src/aes/esp32.rs
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Expand Up @@ -56,7 +56,7 @@ impl<'d> Aes<'d> {
}

pub(super) fn write_start(&mut self) {
self.aes.start().write(|w| w.start().set_bit())
self.aes.start().write(|w| w.start().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
Expand Down
4 changes: 2 additions & 2 deletions esp-hal/src/aes/esp32cX.rs
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Expand Up @@ -13,7 +13,7 @@ impl Aes<'_> {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
}
};
}

pub(super) fn write_key(&mut self, key: &[u8]) {
Expand All @@ -34,7 +34,7 @@ impl Aes<'_> {
}

pub(super) fn write_start(&mut self) {
self.aes.trigger().write(|w| w.trigger().set_bit())
self.aes.trigger().write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
Expand Down
4 changes: 2 additions & 2 deletions esp-hal/src/aes/esp32s2.rs
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Expand Up @@ -21,7 +21,7 @@ impl<'d> Aes<'d> {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
}
};
}

pub(super) fn write_key(&mut self, key: &[u8]) {
Expand Down Expand Up @@ -67,7 +67,7 @@ impl<'d> Aes<'d> {
}

pub(super) fn write_start(&mut self) {
self.aes.trigger().write(|w| w.trigger().set_bit())
self.aes.trigger().write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
Expand Down
4 changes: 2 additions & 2 deletions esp-hal/src/aes/esp32s3.rs
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Expand Up @@ -13,7 +13,7 @@ impl<'d> Aes<'d> {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
}
};
}

pub(super) fn write_key(&mut self, key: &[u8]) {
Expand All @@ -39,7 +39,7 @@ impl<'d> Aes<'d> {
}

pub(super) fn write_start(&mut self) {
self.aes.trigger().write(|w| w.trigger().set_bit())
self.aes.trigger().write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
Expand Down
2 changes: 1 addition & 1 deletion esp-hal/src/clock/clocks_ll/esp32c6.rs
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Expand Up @@ -244,7 +244,7 @@ fn clk_ll_mspi_fast_set_hs_divider(divider: u32) {
.mspi_clk_conf()
.modify(|_, w| w.mspi_fast_hs_div_num().bits(5)),
_ => panic!("Unsupported HS MSPI_FAST divider"),
}
};
}
}

Expand Down
6 changes: 3 additions & 3 deletions esp-hal/src/dma/gdma.rs
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Expand Up @@ -216,7 +216,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaTxInterrupt> for ChannelTxImpl<C> {
};
}
w
})
});
}

fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
Expand Down Expand Up @@ -250,7 +250,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaTxInterrupt> for ChannelTxImpl<C> {
};
}
w
})
});
}

fn pending_interrupts(&self) -> EnumSet<DmaTxInterrupt> {
Expand Down Expand Up @@ -438,7 +438,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaRxInterrupt> for ChannelRxImpl<C> {
};
}
w
})
});
}

fn pending_interrupts(&self) -> EnumSet<DmaRxInterrupt> {
Expand Down
16 changes: 8 additions & 8 deletions esp-hal/src/dma/pdma.rs
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Expand Up @@ -124,7 +124,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaTxInte
};
}
w
})
});
}

fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
Expand Down Expand Up @@ -160,7 +160,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaTxInte
};
}
w
})
});
}

fn pending_interrupts(&self) -> EnumSet<DmaTxInterrupt> {
Expand Down Expand Up @@ -259,7 +259,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaRxInte
};
}
w
})
});
}

fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
Expand Down Expand Up @@ -299,7 +299,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaRxInte
};
}
w
})
});
}

fn pending_interrupts(&self) -> EnumSet<DmaRxInterrupt> {
Expand Down Expand Up @@ -535,7 +535,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaTxInte
};
}
w
})
});
}

fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
Expand Down Expand Up @@ -592,7 +592,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaTxInte
};
}
w
})
});
}

fn waker(&self) -> &'static AtomicWaker {
Expand Down Expand Up @@ -676,7 +676,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaRxInte
};
}
w
})
});
}

fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
Expand Down Expand Up @@ -740,7 +740,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaRxInte
};
}
w
})
});
}

fn waker(&self) -> &'static AtomicWaker {
Expand Down
10 changes: 2 additions & 8 deletions esp-hal/src/i2c/master/mod.rs
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Expand Up @@ -1091,13 +1091,7 @@ fn async_handler(info: &Info, state: &State) {
#[cfg(not(any(esp32, esp32s2)))]
w.txfifo_wm().clear_bit();

cfg_if::cfg_if! {
if #[cfg(esp32)] {
w.ack_err().clear_bit()
} else {
w.nack().clear_bit()
}
}
w.nack().clear_bit()
});

state.waker.wake();
Expand Down Expand Up @@ -1867,7 +1861,7 @@ impl Driver<'_> {
// Handle error cases
let retval = if interrupts.time_out().bit_is_set() {
Err(Error::TimeOut)
} else if interrupts.ack_err().bit_is_set() {
} else if interrupts.nack().bit_is_set() {
Err(Error::AckCheckFailed)
} else if interrupts.arbitration_lost().bit_is_set() {
Err(Error::ArbitrationLost)
Expand Down
4 changes: 2 additions & 2 deletions esp-hal/src/interrupt/software.rs
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Expand Up @@ -93,7 +93,7 @@ impl<const NUM: u8> SoftwareInterrupt<NUM> {
.cpu_intr_from_cpu_3()
.write(|w| w.cpu_intr_from_cpu_3().set_bit()),
_ => unreachable!(),
}
};
}

/// Resets this software-interrupt
Expand All @@ -120,7 +120,7 @@ impl<const NUM: u8> SoftwareInterrupt<NUM> {
.cpu_intr_from_cpu_3()
.write(|w| w.cpu_intr_from_cpu_3().clear_bit()),
_ => unreachable!(),
}
};
}

/// Unsafely create an instance of this peripheral out of thin air.
Expand Down
12 changes: 6 additions & 6 deletions esp-hal/src/mcpwm/operator.rs
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Expand Up @@ -313,7 +313,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,

// SAFETY:
// `bits` is a valid bit pattern
ch.gen((!IS_A) as usize).write(|w| unsafe { w.bits(bits) })
ch.gen((!IS_A) as usize).write(|w| unsafe { w.bits(bits) });
}

/// Set how a new timestamp syncs with the timer
Expand All @@ -334,7 +334,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,
} else {
w.b_upmethod().bits(bits)
}
})
});
}

/// Write a new timestamp.
Expand All @@ -347,16 +347,16 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,

#[cfg(esp32s3)]
if IS_A {
ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) })
ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) });
} else {
ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) })
ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) });
}

#[cfg(any(esp32, esp32c6, esp32h2))]
if IS_A {
ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) })
ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) });
} else {
ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) })
ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) });
}
}

Expand Down
6 changes: 3 additions & 3 deletions esp-hal/src/rsa/esp32cX.rs
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Expand Up @@ -26,7 +26,7 @@ impl<DM: crate::Mode> Rsa<'_, DM> {
/// When enabled rsa peripheral would generate an interrupt when a operation
/// is finished.
pub fn enable_disable_interrupt(&mut self, enable: bool) {
self.rsa.int_ena().write(|w| w.int_ena().bit(enable))
self.rsa.int_ena().write(|w| w.int_ena().bit(enable));
}

fn write_mode(&mut self, mode: u32) {
Expand All @@ -52,7 +52,7 @@ impl<DM: crate::Mode> Rsa<'_, DM> {
.rsa
.search_enable()
.write(|w| w.search_enable().clear_bit()),
}
};
}

/// Checks if the search functionality is enabled in the RSA hardware.
Expand Down Expand Up @@ -87,7 +87,7 @@ impl<DM: crate::Mode> Rsa<'_, DM> {
.rsa
.constant_time()
.write(|w| w.constant_time().set_bit()),
}
};
}

/// Starts the modular exponentiation operation.
Expand Down
6 changes: 3 additions & 3 deletions esp-hal/src/rsa/esp32sX.rs
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Expand Up @@ -27,7 +27,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
/// When enabled rsa peripheral would generate an interrupt when a operation
/// is finished.
pub fn enable_disable_interrupt(&mut self, enable: bool) {
self.rsa.int_ena().write(|w| w.int_ena().bit(enable))
self.rsa.int_ena().write(|w| w.int_ena().bit(enable));
}

fn write_mode(&mut self, mode: u32) {
Expand All @@ -53,7 +53,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
.rsa
.search_enable()
.write(|w| w.search_enable().clear_bit()),
}
};
}

/// Checks if the search functionality is enabled in the RSA hardware.
Expand Down Expand Up @@ -88,7 +88,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
.rsa
.constant_time()
.write(|w| w.constant_time().set_bit()),
}
};
}

/// Starts the modular exponentiation operation.
Expand Down
8 changes: 4 additions & 4 deletions esp-hal/src/rtc_cntl/mod.rs
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Expand Up @@ -983,7 +983,7 @@ impl Rwdt {
RwdtStage::Stage3 => rtc_cntl
.wdtconfig4()
.modify(|_, w| w.wdt_stg3_hold().bits(timeout_raw)),
}
};

#[cfg(any(esp32c6, esp32h2))]
match stage {
Expand All @@ -1003,7 +1003,7 @@ impl Rwdt {
w.wdt_stg3_hold()
.bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier()))
}),
}
};

#[cfg(not(any(esp32, esp32c6, esp32h2)))]
match stage {
Expand All @@ -1023,7 +1023,7 @@ impl Rwdt {
w.wdt_stg3_hold()
.bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier()))
}),
}
};
}

self.set_write_protection(true);
Expand All @@ -1048,7 +1048,7 @@ impl Rwdt {
RwdtStage::Stage3 => rtc_cntl
.wdtconfig0()
.modify(|_, w| unsafe { w.wdt_stg3().bits(action as u8) }),
}
};

self.set_write_protection(true);
}
Expand Down
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