feat(uart): config option to disable the rx input checks

esp-hal/CHANGELOG.md

@@ -32,6 +32,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `BurstConfig`, a device-specific configuration for configuring DMA transfers in burst mode (#2543)
 - `{DmaRxBuf, DmaTxBuf, DmaRxTxBuf}::set_burst_config` (#2543)
 - ESP32-S2: DMA support for AES (#2699)
+- Added `disable_rx_input_checks` to `uart::Config` for cases like reading LIN Break (#2756)
 
 ### Changed
 

esp-hal/src/uart.rs

@@ -404,6 +404,8 @@ pub struct Config {
     pub rx_fifo_full_threshold: u16,
     /// Optional timeout value for RX operations.
     pub rx_timeout: Option<u8>,
+    /// Optionally disable forced checks on incoming RX data.
+    pub disable_rx_input_checks: bool,
 }
 
 impl Config {
@@ -481,6 +483,12 @@ impl Config {
         self.rx_timeout = timeout;
         self
     }
+
+    /// Disables forced checks on incoming RX inputs.
+    pub fn disable_rx_input_checks(mut self, disable: bool) -> Self {
+        self.disable_rx_input_checks = disable;
+        self
+    }
 }
 
 impl Default for Config {
@@ -493,6 +501,7 @@ impl Default for Config {
             clock_source: Default::default(),
             rx_fifo_full_threshold: UART_FULL_THRESH_DEFAULT,
             rx_timeout: Some(UART_TOUT_THRESH_DEFAULT),
+            disable_rx_input_checks: false,
         }
     }
 }
@@ -1268,9 +1277,11 @@ where
 
         // Setting err_wr_mask stops uart from storing data when data is wrong according
         // to reference manual
-        self.register_block()
-            .conf0()
-            .modify(|_, w| w.err_wr_mask().set_bit());
+        if !config.disable_rx_input_checks {
+            self.register_block()
+                .conf0()
+                .modify(|_, w| w.err_wr_mask().set_bit());
+        }
 
         crate::rom::ets_delay_us(15);
 
@@ -2341,6 +2352,7 @@ impl Info {
         self.change_data_bits(config.data_bits);
         self.change_parity(config.parity);
         self.change_stop_bits(config.stop_bits);
+        self.change_disable_rx_input_checks(config.disable_rx_input_checks);
 
         // Reset Tx/Rx FIFOs
         self.rxfifo_reset();
@@ -2608,6 +2620,12 @@ impl Info {
             .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) });
     }
 
+    fn change_disable_rx_input_checks(&self, disable: bool) {
+        self.register_block()
+            .conf0()
+            .modify(|_, w| w.err_wr_mask().bit(!disable));
+    }
+
     fn rxfifo_reset(&self) {
         fn rxfifo_rst(reg_block: &RegisterBlock, enable: bool) {
             reg_block.conf0().modify(|_, w| w.rxfifo_rst().bit(enable));