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RISC-V: Make atomic emulation opt-in #904

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Nov 10, 2023
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15 changes: 8 additions & 7 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -628,25 +628,26 @@ jobs:
- uses: actions/checkout@v3
- uses: dtolnay/rust-toolchain@v1
with:
target: riscv32imc-unknown-none-elf, riscv32imac-unknown-none-elf
toolchain: stable
components: clippy
- uses: Swatinem/rust-cache@v2

# Run clippy on all packages targeting RISC-V.
- name: clippy (esp-riscv-rt)
run: cargo +stable clippy --manifest-path=esp-riscv-rt/Cargo.toml -- -D warnings
run: cd esp-riscv-rt && cargo +stable clippy -- -D warnings
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NGL I like the idea of checking code using the host architecture less and less

- name: clippy (esp32c2-hal)
run: cargo +stable clippy --manifest-path=esp32c2-hal/Cargo.toml -- -D warnings
run: cd esp32c2-hal && cargo +stable clippy -- -D warnings
- name: clippy (esp32c3-hal)
run: cargo +stable clippy --manifest-path=esp32c3-hal/Cargo.toml -- -D warnings
run: cd esp32c3-hal && cargo +stable clippy -- -D warnings
- name: clippy (esp32c6-hal)
run: cargo +stable clippy --manifest-path=esp32c6-hal/Cargo.toml -- -D warnings
run: cd esp32c6-hal && cargo +stable clippy -- -D warnings
- name: clippy (esp32c6-lp-hal)
run: cargo +stable clippy --manifest-path=esp32c6-lp-hal/Cargo.toml -- -D warnings -A asm-sub-register
run: cd esp32c6-lp-hal && cargo +stable clippy -- -D warnings -A asm-sub-register
- name: clippy (esp32h2-hal)
run: cargo +stable clippy --manifest-path=esp32h2-hal/Cargo.toml -- -D warnings
run: cd esp32h2-hal && cargo +stable clippy -- -D warnings
- name: clippy (esp-ulp-riscv-hal)
run: cargo +stable clippy --manifest-path=esp-ulp-riscv-hal/Cargo.toml --features=esp32s3 -- -D warnings -A asm-sub-register
run: cd esp-ulp-riscv-hal && cargo +stable clippy --features=esp32s3 -- -D warnings -A asm-sub-register

clippy-xtensa:
runs-on: ubuntu-latest
Expand Down
2 changes: 2 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

### Changed

- C2, C3: atomic emulation trap is now opt-in (#904)

### Fixed

- ESP32-C2/C3 examples: fix build error (#899)
Expand Down
21 changes: 14 additions & 7 deletions esp-hal-common/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -33,17 +33,20 @@ strum = { version = "0.25.0", default-features = false, features
void = { version = "1.0.2", default-features = false }
usb-device = { version = "0.2.9", optional = true }

# atomic polyfill options
portable-atomic = { version = "1.5.1", default-features = false, optional = true }
riscv-atomic-emulation-trap = { version = "0.4.1", optional = true }

# async
embedded-hal-async = { version = "=1.0.0-rc.1", optional = true }
embedded-io-async = { version = "0.6.0", optional = true }
embassy-executor = { version = "0.3.0", optional = true, features = ["integrated-timers"] }
embassy-executor = { version = "0.3.2", optional = true, features = ["integrated-timers"] }
embassy-futures = { version = "0.1.0", optional = true }
embassy-sync = { version = "0.3.0", optional = true }
embassy-sync = { version = "0.4.0", optional = true }
embassy-time = { version = "0.1.5", optional = true, features = ["nightly"] }

# RISC-V
esp-riscv-rt = { version = "0.5.0", optional = true, path = "../esp-riscv-rt" }
riscv-atomic-emulation-trap = { version = "0.4.1", optional = true }

# Xtensa
xtensa-lx = { version = "0.8.0", optional = true }
Expand All @@ -69,11 +72,11 @@ serde = { version = "1.0.190", features = ["derive"] }

[features]
esp32 = ["xtensa", "esp32/rt", "procmacros/esp32", "xtensa-lx/esp32", "xtensa-lx-rt/esp32"]
esp32c2 = ["riscv", "esp32c2/rt", "procmacros/esp32c2"]
esp32c3 = ["riscv", "esp32c3/rt", "procmacros/esp32c3"]
esp32c2 = ["riscv", "esp32c2/rt", "procmacros/esp32c2", "portable-atomic?/unsafe-assume-single-core"]
esp32c3 = ["riscv", "esp32c3/rt", "procmacros/esp32c3", "portable-atomic?/unsafe-assume-single-core"]
esp32c6 = ["riscv", "esp32c6/rt", "procmacros/esp32c6"]
esp32h2 = ["riscv", "esp32h2/rt", "procmacros/esp32h2"]
esp32s2 = ["xtensa", "esp32s2/rt", "procmacros/esp32s2", "xtensa-lx/esp32s2", "xtensa-lx-rt/esp32s2", "usb-otg"]
esp32s2 = ["xtensa", "esp32s2/rt", "procmacros/esp32s2", "xtensa-lx/esp32s2", "xtensa-lx-rt/esp32s2", "usb-otg", "portable-atomic?/unsafe-assume-single-core"]
esp32s3 = ["xtensa", "esp32s3/rt", "procmacros/esp32s3", "xtensa-lx/esp32s3", "xtensa-lx-rt/esp32s3", "usb-otg"]

# Crystal frequency selection (ESP32 and ESP32-C2 only!)
Expand Down Expand Up @@ -125,9 +128,13 @@ embassy-time-systick = []
embassy-time-timg0 = []

# Architecture-specific features (intended for internal use)
riscv = ["critical-section/restore-state-u8", "esp-riscv-rt", "esp-riscv-rt/zero-bss", "riscv-atomic-emulation-trap"]
riscv = ["critical-section/restore-state-u8", "esp-riscv-rt", "esp-riscv-rt/zero-bss"]
xtensa = ["critical-section/restore-state-u32"]

portable-atomic = ["dep:portable-atomic"]
riscv-atomic-emulation = ["dep:riscv-atomic-emulation-trap", "atomic-emulation"]
atomic-emulation = []

# Initialize / clear data sections and RTC memory
rv-init-data = ["esp-riscv-rt/init-data", "esp-riscv-rt/init-rw-text"]
rv-zero-rtc-bss = ["esp-riscv-rt/zero-rtc-fast-bss"]
Expand Down
22 changes: 22 additions & 0 deletions esp-hal-common/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,28 @@ fn main() -> Result<(), Box<dyn Error>> {
unreachable!() // We've confirmed exactly one known device was selected
};

// The C6 has an "atomic" peripheral but it's an exception, not the rule
// For S2, we just keep lying for now. The target has emulation support
// force-enabled.
let has_native_atomic_support = matches!(
device_name,
"esp32" | "esp32s2" | "esp32s3" | "esp32c6" | "esp32h2"
);

let atomic_emulation_enabled = cfg!(feature = "atomic-emulation");
let portable_atomic_enabled = cfg!(feature = "portable-atomic");

if atomic_emulation_enabled && portable_atomic_enabled {
panic!("The `atomic-emulation` and `portable-atomic` features cannot be used together");
}

if has_native_atomic_support {
if atomic_emulation_enabled {
println!("cargo:warning={} has native atomic instructions, the `atomic-emulation` feature is not needed", device_name);
}
println!("cargo:rustc-cfg=has_native_atomic_support");
}

// Load the configuration file for the configured device:
let chip_toml_path = PathBuf::from(env!("CARGO_MANIFEST_DIR"))
.join("devices")
Expand Down
10 changes: 4 additions & 6 deletions esp-hal-common/src/analog/adc/riscv.rs
Original file line number Diff line number Diff line change
Expand Up @@ -687,8 +687,6 @@ macro_rules! impl_adc_interface {
}
}

pub use implementation::*;

#[cfg(esp32c2)]
mod implementation {
//! # Analog to digital (ADC) conversion support.
Expand Down Expand Up @@ -722,7 +720,7 @@ mod implementation {
//! }
//! ```

pub use crate::analog::ADC1;
use crate::analog::ADC1;

impl_adc_interface! {
ADC1 [
Expand Down Expand Up @@ -769,7 +767,7 @@ mod implementation {
//! }
//! ```

pub use crate::analog::{ADC1, ADC2};
use crate::analog::{ADC1, ADC2};

impl_adc_interface! {
ADC1 [
Expand Down Expand Up @@ -821,7 +819,7 @@ mod implementation {
//! }
//! ```

pub use crate::analog::ADC1;
use crate::analog::ADC1;

impl_adc_interface! {
ADC1 [
Expand Down Expand Up @@ -869,7 +867,7 @@ mod implementation {
//! }
//! ```

pub use crate::analog::ADC1;
use crate::analog::ADC1;

impl_adc_interface! {
ADC1 [
Expand Down
6 changes: 6 additions & 0 deletions esp-hal-common/src/dma/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1153,11 +1153,13 @@ pub(crate) mod asynch {
}
}

#[cfg(any(i2s0, i2s1))]
pub struct DmaTxDoneChFuture<'a, TX> {
pub(crate) tx: &'a mut TX,
_a: (),
}

#[cfg(any(i2s0, i2s1))]
impl<'a, TX> DmaTxDoneChFuture<'a, TX>
where
TX: Tx,
Expand All @@ -1168,6 +1170,7 @@ pub(crate) mod asynch {
}
}

#[cfg(any(i2s0, i2s1))]
impl<'a, TX> core::future::Future for DmaTxDoneChFuture<'a, TX>
where
TX: Tx,
Expand All @@ -1187,11 +1190,13 @@ pub(crate) mod asynch {
}
}

#[cfg(any(i2s0, i2s1))]
pub struct DmaRxDoneChFuture<'a, RX> {
pub(crate) rx: &'a mut RX,
_a: (),
}

#[cfg(any(i2s0, i2s1))]
impl<'a, RX> DmaRxDoneChFuture<'a, RX>
where
RX: Rx,
Expand All @@ -1202,6 +1207,7 @@ pub(crate) mod asynch {
}
}

#[cfg(any(i2s0, i2s1))]
impl<'a, RX> core::future::Future for DmaRxDoneChFuture<'a, RX>
where
RX: Rx,
Expand Down
14 changes: 7 additions & 7 deletions esp-hal-common/src/embassy/executor/xtensa/interrupt.rs
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
//! Multicore-aware interrupt-mode executor.
use core::{
cell::UnsafeCell,
marker::PhantomData,
mem::MaybeUninit,
sync::atomic::{AtomicUsize, Ordering},
};
use core::{cell::UnsafeCell, marker::PhantomData, mem::MaybeUninit};

use embassy_executor::{raw, SendSpawner};

use crate::{get_core, interrupt, peripherals, peripherals::SYSTEM};
use crate::{
atomic::{AtomicUsize, Ordering},
get_core,
interrupt,
peripherals::{self, SYSTEM},
};

static FROM_CPU_IRQ_USED: AtomicUsize = AtomicUsize::new(0);

Expand Down
11 changes: 6 additions & 5 deletions esp-hal-common/src/embassy/executor/xtensa/thread.rs
Original file line number Diff line number Diff line change
@@ -1,12 +1,13 @@
//! Multicore-aware thread-mode embassy executor.
use core::{
marker::PhantomData,
sync::atomic::{AtomicBool, Ordering},
};
use core::marker::PhantomData;

use embassy_executor::{raw, Spawner};

use crate::{get_core, prelude::interrupt};
use crate::{
atomic::{AtomicBool, Ordering},
get_core,
prelude::interrupt,
};
#[cfg(multi_core)]
use crate::{
interrupt,
Expand Down
6 changes: 3 additions & 3 deletions esp-hal-common/src/embassy/time_driver_timg.rs
Original file line number Diff line number Diff line change
Expand Up @@ -86,15 +86,15 @@ impl EmbassyTimer {

pub(crate) fn set_alarm(
&self,
alarm: embassy_time::driver::AlarmHandle,
_alarm: embassy_time::driver::AlarmHandle,
timestamp: u64,
) -> bool {
critical_section::with(|cs| {
critical_section::with(|_cs| {
// The hardware fires the alarm even if timestamp is lower than the current
// time. In this case the interrupt handler will pend a wakeup when we exit the
// critical section.
#[cfg(any(esp32, esp32s2, esp32s3))]
if alarm.id() == 1 {
if _alarm.id() == 1 {
let mut tg = unsafe { Timer1::<TIMG0>::steal() };
Self::arm(&mut tg, timestamp);
return;
Expand Down
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