Re-generate PAC

esp32s2/src/copy_dma.rs

@@ -0,0 +1,180 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    int_raw: INT_RAW,
+    int_st: INT_ST,
+    int_ena: INT_ENA,
+    int_clr: INT_CLR,
+    out_link: OUT_LINK,
+    in_link: IN_LINK,
+    out_eof_des_addr: OUT_EOF_DES_ADDR,
+    in_eof_des_addr: IN_EOF_DES_ADDR,
+    out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR,
+    inlink_dscr: INLINK_DSCR,
+    inlink_dscr_bf0: INLINK_DSCR_BF0,
+    _reserved11: [u8; 0x04],
+    outlink_dscr: OUTLINK_DSCR,
+    outlink_dscr_bf0: OUTLINK_DSCR_BF0,
+    _reserved13: [u8; 0x04],
+    conf: CONF,
+    in_st: IN_ST,
+    out_st: OUT_ST,
+    _reserved16: [u8; 0xb4],
+    date: DATE,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Raw interrupt status"]
+    #[inline(always)]
+    pub const fn int_raw(&self) -> &INT_RAW {
+        &self.int_raw
+    }
+    #[doc = "0x04 - Masked interrupt status"]
+    #[inline(always)]
+    pub const fn int_st(&self) -> &INT_ST {
+        &self.int_st
+    }
+    #[doc = "0x08 - Interrupt enable bits"]
+    #[inline(always)]
+    pub const fn int_ena(&self) -> &INT_ENA {
+        &self.int_ena
+    }
+    #[doc = "0x0c - Interrupt clear bits"]
+    #[inline(always)]
+    pub const fn int_clr(&self) -> &INT_CLR {
+        &self.int_clr
+    }
+    #[doc = "0x10 - Link descriptor address and control"]
+    #[inline(always)]
+    pub const fn out_link(&self) -> &OUT_LINK {
+        &self.out_link
+    }
+    #[doc = "0x14 - Link descriptor address and control"]
+    #[inline(always)]
+    pub const fn in_link(&self) -> &IN_LINK {
+        &self.in_link
+    }
+    #[doc = "0x18 - Transmit descriptor address when EOF occurs"]
+    #[inline(always)]
+    pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR {
+        &self.out_eof_des_addr
+    }
+    #[doc = "0x1c - Receive descriptor address when EOF occurs"]
+    #[inline(always)]
+    pub const fn in_eof_des_addr(&self) -> &IN_EOF_DES_ADDR {
+        &self.in_eof_des_addr
+    }
+    #[doc = "0x20 - Transmit descriptor address before the last transmit descriptor"]
+    #[inline(always)]
+    pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR {
+        &self.out_eof_bfr_des_addr
+    }
+    #[doc = "0x24 - Address of current receive descriptor"]
+    #[inline(always)]
+    pub const fn inlink_dscr(&self) -> &INLINK_DSCR {
+        &self.inlink_dscr
+    }
+    #[doc = "0x28 - Address of last receive descriptor"]
+    #[inline(always)]
+    pub const fn inlink_dscr_bf0(&self) -> &INLINK_DSCR_BF0 {
+        &self.inlink_dscr_bf0
+    }
+    #[doc = "0x30 - Address of current transmit descriptor"]
+    #[inline(always)]
+    pub const fn outlink_dscr(&self) -> &OUTLINK_DSCR {
+        &self.outlink_dscr
+    }
+    #[doc = "0x34 - Address of last transmit descriptor"]
+    #[inline(always)]
+    pub const fn outlink_dscr_bf0(&self) -> &OUTLINK_DSCR_BF0 {
+        &self.outlink_dscr_bf0
+    }
+    #[doc = "0x3c - Copy DMA configuration register"]
+    #[inline(always)]
+    pub const fn conf(&self) -> &CONF {
+        &self.conf
+    }
+    #[doc = "0x40 - Status register of receiving data"]
+    #[inline(always)]
+    pub const fn in_st(&self) -> &IN_ST {
+        &self.in_st
+    }
+    #[doc = "0x44 - Status register of transmitting data"]
+    #[inline(always)]
+    pub const fn out_st(&self) -> &OUT_ST {
+        &self.out_st
+    }
+    #[doc = "0xfc - Copy DMA version control register"]
+    #[inline(always)]
+    pub const fn date(&self) -> &DATE {
+        &self.date
+    }
+}
+#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
+pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
+#[doc = "Raw interrupt status"]
+pub mod int_raw;
+#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
+pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
+#[doc = "Masked interrupt status"]
+pub mod int_st;
+#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
+pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
+#[doc = "Interrupt enable bits"]
+pub mod int_ena;
+#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
+#[doc = "Interrupt clear bits"]
+pub mod int_clr;
+#[doc = "OUT_LINK (rw) register accessor: Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link`] module"]
+pub type OUT_LINK = crate::Reg<out_link::OUT_LINK_SPEC>;
+#[doc = "Link descriptor address and control"]
+pub mod out_link;
+#[doc = "IN_LINK (rw) register accessor: Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link`] module"]
+pub type IN_LINK = crate::Reg<in_link::IN_LINK_SPEC>;
+#[doc = "Link descriptor address and control"]
+pub mod in_link;
+#[doc = "CONF (r) register accessor: Copy DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"]
+pub type CONF = crate::Reg<conf::CONF_SPEC>;
+#[doc = "Copy DMA configuration register"]
+pub mod conf;
+#[doc = "OUT_EOF_DES_ADDR (r) register accessor: Transmit descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr`] module"]
+pub type OUT_EOF_DES_ADDR = crate::Reg<out_eof_des_addr::OUT_EOF_DES_ADDR_SPEC>;
+#[doc = "Transmit descriptor address when EOF occurs"]
+pub mod out_eof_des_addr;
+#[doc = "IN_EOF_DES_ADDR (r) register accessor: Receive descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`in_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_eof_des_addr`] module"]
+pub type IN_EOF_DES_ADDR = crate::Reg<in_eof_des_addr::IN_EOF_DES_ADDR_SPEC>;
+#[doc = "Receive descriptor address when EOF occurs"]
+pub mod in_eof_des_addr;
+#[doc = "OUT_EOF_BFR_DES_ADDR (r) register accessor: Transmit descriptor address before the last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr`] module"]
+pub type OUT_EOF_BFR_DES_ADDR = crate::Reg<out_eof_bfr_des_addr::OUT_EOF_BFR_DES_ADDR_SPEC>;
+#[doc = "Transmit descriptor address before the last transmit descriptor"]
+pub mod out_eof_bfr_des_addr;
+#[doc = "INLINK_DSCR (r) register accessor: Address of current receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`inlink_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inlink_dscr`] module"]
+pub type INLINK_DSCR = crate::Reg<inlink_dscr::INLINK_DSCR_SPEC>;
+#[doc = "Address of current receive descriptor"]
+pub mod inlink_dscr;
+#[doc = "INLINK_DSCR_BF0 (r) register accessor: Address of last receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`inlink_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inlink_dscr_bf0`] module"]
+pub type INLINK_DSCR_BF0 = crate::Reg<inlink_dscr_bf0::INLINK_DSCR_BF0_SPEC>;
+#[doc = "Address of last receive descriptor"]
+pub mod inlink_dscr_bf0;
+#[doc = "OUTLINK_DSCR (r) register accessor: Address of current transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`outlink_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outlink_dscr`] module"]
+pub type OUTLINK_DSCR = crate::Reg<outlink_dscr::OUTLINK_DSCR_SPEC>;
+#[doc = "Address of current transmit descriptor"]
+pub mod outlink_dscr;
+#[doc = "OUTLINK_DSCR_BF0 (r) register accessor: Address of last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`outlink_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outlink_dscr_bf0`] module"]
+pub type OUTLINK_DSCR_BF0 = crate::Reg<outlink_dscr_bf0::OUTLINK_DSCR_BF0_SPEC>;
+#[doc = "Address of last transmit descriptor"]
+pub mod outlink_dscr_bf0;
+#[doc = "IN_ST (r) register accessor: Status register of receiving data\n\nYou can [`read`](crate::Reg::read) this register and get [`in_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_st`] module"]
+pub type IN_ST = crate::Reg<in_st::IN_ST_SPEC>;
+#[doc = "Status register of receiving data"]
+pub mod in_st;
+#[doc = "OUT_ST (r) register accessor: Status register of transmitting data\n\nYou can [`read`](crate::Reg::read) this register and get [`out_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_st`] module"]
+pub type OUT_ST = crate::Reg<out_st::OUT_ST_SPEC>;
+#[doc = "Status register of transmitting data"]
+pub mod out_st;
+#[doc = "DATE (rw) register accessor: Copy DMA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
+pub type DATE = crate::Reg<date::DATE_SPEC>;
+#[doc = "Copy DMA version control register"]
+pub mod date;

esp32s2/src/copy_dma/conf.rs

@@ -0,0 +1,129 @@
+#[doc = "Register `CONF` reader"]
+pub type R = crate::R<CONF_SPEC>;
+#[doc = "Field `IN_RST` reader - Set this bit to reset in DMA FSM."]
+pub type IN_RST_R = crate::BitReader;
+#[doc = "Field `OUT_RST` reader - Set this bit to reset out DMA FSM."]
+pub type OUT_RST_R = crate::BitReader;
+#[doc = "Field `CMDFIFO_RST` reader - Set this bit to reset in_cmd FIFO and out_cmd FIFO."]
+pub type CMDFIFO_RST_R = crate::BitReader;
+#[doc = "Field `FIFO_RST` reader - Set this bit to reset data in RX FIFO."]
+pub type FIFO_RST_R = crate::BitReader;
+#[doc = "Field `OUT_OWNER` reader - This is used to configure the owner bit in transmit descriptor. This is effective only when you set OUT_AUTO_WRBACK."]
+pub type OUT_OWNER_R = crate::BitReader;
+#[doc = "Field `IN_OWNER` reader - This is used to configure the owner bit in receive descriptor."]
+pub type IN_OWNER_R = crate::BitReader;
+#[doc = "Field `OUT_AUTO_WRBACK` reader - This bit is used to write back out descriptor when hardware has already used this descriptor."]
+pub type OUT_AUTO_WRBACK_R = crate::BitReader;
+#[doc = "Field `CHECK_OWNER` reader - Set this bit to enable owner bit check in descriptor."]
+pub type CHECK_OWNER_R = crate::BitReader;
+#[doc = "1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CLK_EN {
+    #[doc = "0: Support clock only when application writes registers"]
+    OnWrite = 0,
+    #[doc = "1: Force clock on for register"]
+    Force = 1,
+}
+impl From<CLK_EN> for bool {
+    #[inline(always)]
+    fn from(variant: CLK_EN) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CLK_EN` reader - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers."]
+pub type CLK_EN_R = crate::BitReader<CLK_EN>;
+impl CLK_EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CLK_EN {
+        match self.bits {
+            false => CLK_EN::OnWrite,
+            true => CLK_EN::Force,
+        }
+    }
+    #[doc = "Support clock only when application writes registers"]
+    #[inline(always)]
+    pub fn is_on_write(&self) -> bool {
+        *self == CLK_EN::OnWrite
+    }
+    #[doc = "Force clock on for register"]
+    #[inline(always)]
+    pub fn is_force(&self) -> bool {
+        *self == CLK_EN::Force
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Set this bit to reset in DMA FSM."]
+    #[inline(always)]
+    pub fn in_rst(&self) -> IN_RST_R {
+        IN_RST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set this bit to reset out DMA FSM."]
+    #[inline(always)]
+    pub fn out_rst(&self) -> OUT_RST_R {
+        OUT_RST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to reset in_cmd FIFO and out_cmd FIFO."]
+    #[inline(always)]
+    pub fn cmdfifo_rst(&self) -> CMDFIFO_RST_R {
+        CMDFIFO_RST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to reset data in RX FIFO."]
+    #[inline(always)]
+    pub fn fifo_rst(&self) -> FIFO_RST_R {
+        FIFO_RST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - This is used to configure the owner bit in transmit descriptor. This is effective only when you set OUT_AUTO_WRBACK."]
+    #[inline(always)]
+    pub fn out_owner(&self) -> OUT_OWNER_R {
+        OUT_OWNER_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - This is used to configure the owner bit in receive descriptor."]
+    #[inline(always)]
+    pub fn in_owner(&self) -> IN_OWNER_R {
+        IN_OWNER_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This bit is used to write back out descriptor when hardware has already used this descriptor."]
+    #[inline(always)]
+    pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R {
+        OUT_AUTO_WRBACK_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set this bit to enable owner bit check in descriptor."]
+    #[inline(always)]
+    pub fn check_owner(&self) -> CHECK_OWNER_R {
+        CHECK_OWNER_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 31 - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers."]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF")
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("cmdfifo_rst", &self.cmdfifo_rst())
+            .field("fifo_rst", &self.fifo_rst())
+            .field("out_owner", &self.out_owner())
+            .field("in_owner", &self.in_owner())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("check_owner", &self.check_owner())
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+#[doc = "Copy DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF_SPEC;
+impl crate::RegisterSpec for CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
+impl crate::Readable for CONF_SPEC {}
+#[doc = "`reset()` method sets CONF to value 0"]
+impl crate::Resettable for CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

esp32s2/src/copy_dma/date.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DMA_DATE` reader - This is the version control register."]
+pub type DMA_DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DMA_DATE` writer - This is the version control register."]
+pub type DMA_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - This is the version control register."]
+    #[inline(always)]
+    pub fn dma_date(&self) -> DMA_DATE_R {
+        DMA_DATE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE")
+            .field("dma_date", &self.dma_date())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This is the version control register."]
+    #[inline(always)]
+    pub fn dma_date(&mut self) -> DMA_DATE_W<DATE_SPEC> {
+        DMA_DATE_W::new(self, 0)
+    }
+}
+#[doc = "Copy DMA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x1808_2000"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x1808_2000;
+}