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Resource Constrained Neural Network Running Digit Recognition on FPGA

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Aether Engine

A Parameterized CNN Accelerator for FPGAs with Resource-Aware Scaling

Overview

Aether Engine is a versatile CNN accelerator implementation for FPGAs that supports various neural network architectures. The accelerator is designed with flexibility in mind, allowing customization for both resource-constrained and high-performance FPGA targets.

Key Features

  • Parameterized design supporting various matrix sizes
  • Scalable number of accelerator units
  • Configurable for different FPGA resource profiles
  • Support for variable input dimensions
  • Flexible CNN operation support

Supported Operations

  • Convolution layers
  • Activation functions
    • Sigmoid
    • ReLU
    • Softmax
  • Dense (Fully connected) layers
  • Maxpooling

Tested Models

  • MNIST (In Progress)
  • YOLO (Planned)

Build Instructions

git clone --recurse-submodules https://github.com/fpgabuilds/mnist-fpga.git

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Resource Constrained Neural Network Running Digit Recognition on FPGA

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