a

README.md

@@ -0,0 +1,12 @@
+# Todo
+- pma
+- pmp
+- io stuff
+    - clint
+    - plic
+    - uart
+
+# Goals
+- xv6
+- linux
+- make it stupidly fast

emu/src/cpu/mod.rs

@@ -8,7 +8,6 @@ mod mmu;
 
 pub struct Cpu<'a> {
     bus: &'a mut bus::Bus<'a>,
-    io: &'a mut io::Io,
 
     regs: [u64; 31],
     float_regs: [u64; 32],
@@ -21,10 +20,9 @@ pub struct Cpu<'a> {
 }
 
 impl<'a> Cpu<'a> {
-    pub fn new(bus: &'a mut bus::Bus<'a>, io: &'a mut io::Io) -> Self {
+    pub fn new(bus: &'a mut bus::Bus<'a>) -> Self {
         let mut cpu = Self {
             bus,
-            io,
 
             regs: [0; 31],
             float_regs: [0; 32],

emu/src/lib.rs

@@ -1,3 +1,2 @@
 pub mod bus;
 pub mod cpu;
-pub mod io;

src/main.rs

@@ -13,8 +13,7 @@ fn main() {
     let mut ram = std::fs::read(&args.prog).unwrap();
     ram.resize(0x10000, 0);
     let mut bus = emu::bus::Bus::new(&mut ram);
-    let mut io = emu::io::Io::new();
-    let mut cpu = emu::cpu::Cpu::new(&mut bus, &mut io);
+    let mut cpu = emu::cpu::Cpu::new(&mut bus);
 
     loop {
         cpu.step(args.testing);

tests/README

@@ -1 +1 @@
-https://github.com/riscv-software-src/riscv-tests
+Compiled from https://github.com/riscv-software-src/riscv-tests

uart_hello.c

@@ -0,0 +1,18 @@
+int main() {
+    volatile char *uart = (volatile char *) 0x10000000;
+    uart[0] = 'H';
+    uart[0] = 'e';
+    uart[0] = 'l';
+    uart[0] = 'l';
+    uart[0] = 'o';
+    uart[0] = ',';
+    uart[0] = ' ';
+    uart[0] = 'w';
+    uart[0] = 'o';
+    uart[0] = 'r';
+    uart[0] = 'l';
+    uart[0] = 'd';
+    uart[0] = '!';
+    uart[0] = '\n';
+    return 0;
+}