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d ext
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@funnsam
funnsam committed Jun 19, 2024
1 parent 48b4981 commit db068a7
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Showing 3 changed files with 18 additions and 12 deletions.
4 changes: 1 addition & 3 deletions emu/src/cpu/csr.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -76,9 +76,7 @@ impl<'a> Cpu<'a> {
self.check_csr_perm(a, err)?;

Ok(match a {
// TODO:
// D | bit 3
CSR_MISA => 0x8000000000141121, // rv64imaf_su (Z extensions are not in here)
CSR_MISA => 0x8000000000141125, // rv64imafd_su (Z extensions are not in here)
CSR_MHARTID => 0,
CSR_MSTATUS => {
let mut s = self.csrs[a as usize];
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10 changes: 7 additions & 3 deletions emu/src/cpu/float.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -172,8 +172,12 @@ macro_rules! minmax {
}

macro_rules! gen {
($t: tt $width: tt $r: tt $w: tt $rr: tt $rw: tt $cnan: tt) => {
($t: tt $width: tt $r: tt $w: tt $rru: tt $rr: tt $rw: tt $cnan: tt) => {
impl<'a> Cpu<'a> {
pub(crate) fn $rru(&self, n: usize) -> $width {
self.read_float_reg(n) as $width
}

pub(crate) fn $rr(&self, n: usize) -> $width {
let r = self.read_float_reg(n);

Expand All @@ -197,8 +201,8 @@ macro_rules! gen {
};
}

gen!(f32 u32 read_float_reg_f32 write_float_reg_f32 read_float_reg_r32 write_float_reg_r32 F32_CNAN);
gen!(f64 u64 read_float_reg_f64 write_float_reg_f64 read_float_reg_r64 write_float_reg_r64 F64_CNAN);
gen!(f32 u32 read_float_reg_f32 write_float_reg_f32 read_float_reg_r32_uc read_float_reg_r32 write_float_reg_r32 F32_CNAN);
gen!(f64 u64 read_float_reg_f64 write_float_reg_f64 read_float_reg_r64_uc read_float_reg_r64 write_float_reg_r64 F64_CNAN);

// https://github.com/rust-lang/rust/issues/48825
pub(crate) trait Snan {
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16 changes: 10 additions & 6 deletions emu/src/cpu/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -194,8 +194,8 @@ impl<'a> Cpu<'a> {
}};
(_ getrwf f32) => { (Self::read_float_reg_f32, Self::write_float_reg_f32) };
(_ getrwf f64) => { (Self::read_float_reg_f64, Self::write_float_reg_f64) };
(_ getrwf sr2i) => { (Self::read_float_reg_r32, Self::write_reg) };
(_ getrwf dr2i) => { (Self::read_float_reg_r64, Self::write_reg) };
(_ getrwf sru2i) => { (Self::read_float_reg_r32_uc, Self::write_reg) };
(_ getrwf dru2i) => { (Self::read_float_reg_r64_uc, Self::write_reg) };
(_ getrwf f2i) => { (Self::read_float_reg_f32, Self::write_reg) };
(_ getrwf d2i) => { (Self::read_float_reg_f64, Self::write_reg) };
(_ getrwf i2sr) => { (Self::read_reg, Self::write_float_reg_r32) };
Expand All @@ -204,6 +204,8 @@ impl<'a> Cpu<'a> {
(_ getrwf i2d) => { (Self::read_reg, Self::write_float_reg_f64) };
(_ getrwf sr2sr) => { (Self::read_float_reg_r32, Self::write_float_reg_r32) };
(_ getrwf dr2dr) => { (Self::read_float_reg_r64, Self::write_float_reg_r64) };
(_ getrwf f2d) => { (Self::read_float_reg_f32, Self::write_float_reg_f64) };
(_ getrwf d2f) => { (Self::read_float_reg_f64, Self::write_float_reg_f32) };
(fop [$($f7: tt $ty: tt $r2: tt $rm: tt $exec: expr),* $(,)?]) => {{
let r1 = (inst >> 15) & 0x1f;
let r2 = (inst >> 20) & 0x1f;
Expand Down Expand Up @@ -400,8 +402,8 @@ impl<'a> Cpu<'a> {
0x3 write_float_reg_r64 |a, b| Ok(self.mmu_load_u64(a + b)?),
]),
0x27 => exec!(sx [
0x2 read_float_reg_r32 |a, b, c| if self.can_use_fp() { self.mmu_store_u32(a + c, b as _) } else { Ok(()) },
0x3 read_float_reg_r64 |a, b, c| if self.can_use_fp() { self.mmu_store_u64(a + c, b) } else { Ok(()) },
0x2 read_float_reg_r32_uc |a, b, c| if self.can_use_fp() { self.mmu_store_u32(a + c, b as _) } else { Ok(()) },
0x3 read_float_reg_r64_uc |a, b, c| if self.can_use_fp() { self.mmu_store_u64(a + c, b) } else { Ok(()) },
]),
0x43 => exec!(r4f [
f32 |a, b, c| Ok(self.float_do_op_f32(|| a * b + c)),
Expand Down Expand Up @@ -434,7 +436,7 @@ impl<'a> Cpu<'a> {
0x60 f2i 1 _ |a: f32, _| Ok(self.float_do_op(|s| float::cast!(s a f32 u32 u) as i32 as u64)),
0x60 f2i 2 _ |a: f32, _| Ok(self.float_do_op(|s| float::cast!(s a f32 i64 s) as u64)),
0x60 f2i 3 _ |a: f32, _| Ok(self.float_do_op(|s| float::cast!(s a f32 u64 u))),
0x70 sr2i 0 0 |a, _| Ok(a as i32 as u64),
0x70 sru2i 0 0 |a, _| Ok(a as i32 as u64),
0x50 f2i _ 2 |a, b| Ok(self.float_cmp(a, b, a == b, Snan::is_snan)),
0x50 f2i _ 1 |a, b| Ok(self.float_cmp(a, b, a < b, f32::is_nan)),
0x50 f2i _ 0 |a, b| Ok(self.float_cmp(a, b, a <= b, f32::is_nan)),
Expand Down Expand Up @@ -466,11 +468,13 @@ impl<'a> Cpu<'a> {
0x11 dr2dr _ 2 |a, b| Ok((a & 0x7fff_ffff_ffff_ffff) | ((a ^ b) & 0x8000_0000_0000_0000)),
0x15 f64 _ 0 |a: f64, b: f64| Ok(float::minmax!(f64 self a b min)),
0x15 f64 _ 1 |a: f64, b: f64| Ok(float::minmax!(f64 self a b max)),
0x20 d2f 1 _ |a, _| Ok(self.float_do_op_f32(|| a as f32)),
0x21 f2d 0 _ |a, _| Ok(self.float_do_op_f64(|| a as f64)),
0x61 d2i 0 _ |a: f64, _| Ok(self.float_do_op(|s| float::cast!(s a f64 i32 s) as u64)),
0x61 d2i 1 _ |a: f64, _| Ok(self.float_do_op(|s| float::cast!(s a f64 u32 u) as i32 as u64)),
0x61 d2i 2 _ |a: f64, _| Ok(self.float_do_op(|s| float::cast!(s a f64 i64 s) as u64)),
0x61 d2i 3 _ |a: f64, _| Ok(self.float_do_op(|s| float::cast!(s a f64 u64 u))),
0x71 dr2i 0 0 |a, _| Ok(a),
0x71 dru2i 0 0 |a, _| Ok(a),
0x51 d2i _ 2 |a, b| Ok(self.float_cmp(a, b, a == b, Snan::is_snan)),
0x51 d2i _ 1 |a, b| Ok(self.float_cmp(a, b, a < b, f64::is_nan)),
0x51 d2i _ 0 |a, b| Ok(self.float_cmp(a, b, a <= b, f64::is_nan)),
Expand Down

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