feat(laze): add riscv and xtensa modules

future-proof-iot · Sep 10, 2024 · 44fed3b · 44fed3b
1 parent e46f357
commit 44fed3b
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Showing 2 changed files with 21 additions and 6 deletions.
diff --git a/laze-project.yml b/laze-project.yml
@@ -288,6 +288,8 @@ contexts:
 
   - name: esp32c3
     parent: esp
+    selects:
+      - riscv
     env:
       RUSTFLAGS:
         - --cfg context=\"esp32c3\"
@@ -296,6 +298,8 @@ contexts:
 
   - name: esp32c6
     parent: esp
+    selects:
+      - riscv
     env:
       RUSTFLAGS:
         - --cfg context=\"esp32c6\"
@@ -304,6 +308,8 @@ contexts:
 
   - name: esp32s3
     parent: esp
+    selects:
+      - xtensa
     env:
       CARGO_TOOLCHAIN: +esp
       RUSTFLAGS:
@@ -423,6 +429,18 @@ modules:
         RUSTFLAGS:
           - --cfg armv7m
 
+  - name: xtensa
+    env:
+      global:
+        RUSTFLAGS:
+          - --cfg context=\"xtensa\"
+
+  - name: riscv
+    env:
+      global:
+        RUSTFLAGS:
+          - --cfg context=\"riscv\"
+
   - name: rp-link-arg
     help: helper module that ensures link-rp.x is added behind cortex-m ld scripts
     env:

diff --git a/src/riot-rs-threads/src/arch/mod.rs b/src/riot-rs-threads/src/arch/mod.rs
@@ -28,16 +28,13 @@ cfg_if::cfg_if! {
     if #[cfg(context = "cortex-m")] {
         mod cortex_m;
         pub use cortex_m::Cpu;
-    }
-    else if #[cfg(any(context = "esp32c3", context = "esp32c6"))] {
+    } else if #[cfg(context = "riscv")] {
         mod riscv;
         pub use riscv::Cpu;
-    }
-    else if #[cfg(context = "esp32s3")] {
+    } else if #[cfg(context = "xtensa")] {
         mod xtensa;
         pub use xtensa::Cpu;
-    }
-    else {
+    } else {
         pub struct Cpu;
         impl Arch for Cpu {
             type ThreadData = ();