Document community register aliases and recently identified registers

src/Audio.md

@@ -54,7 +54,7 @@ The SGB2 rectifies this issue.
 All interfaces to the APU use **durations** instead of frequencies, which may be confusing as signal theory and music are more typically based on the latter.
 Thus, durations will be expressed from their frequencies: for example, a "256 Hz tick" means "1 ∕ 256th of a second".
 
-The length of APU ticks is not affected by [CGB double speed](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>), so the APU works just the same regardless of CPU speed.
+The length of APU ticks is not affected by [CGB double speed](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>), so the APU works just the same regardless of CPU speed.
 
 :::warning Terminology
 

src/Audio_Registers.md

@@ -12,7 +12,7 @@ As a rule of thumb, for any `x` in `1`, `2`, `3`, `4`:
 
 ...but there are some exceptions.
 
-One of the pitfalls of the `NRxy` naming convention is that the register's purpose is not immediately clear from its name, so some alternative names have been proposed, [such as `AUDENA` for `NR52`](https://github.com/gbdev/hardware.inc/blob/05f5a9b6c7172abe1d7488080c1c050284c09226/hardware.inc#L415).
+One of the pitfalls of the `NRxy` naming convention is that the register's purpose is not immediately clear from its name, so some alternative `AUD*` names have been proposed, [such as `AUDENA` for `NR52`](https://github.com/gbdev/hardware.inc/blob/8d4432e5796bffe2e13c438013285c5f11c37b99/hardware.inc#L910).
 
 ## Global control registers
 

src/Audio_details.md

@@ -84,7 +84,7 @@ Same, but with channels 3 and 4.
 
 ### DIV-APU
 
-A "DIV-APU" counter is increased every time `DIV`'s bit 4 (5 in [double-speed mode](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>)) goes from 1 to 0, therefore at a frequency of 512 Hz (regardless of whether double-speed is active).
+A "DIV-APU" counter is increased every time `DIV`'s bit 4 (5 in [double-speed mode](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>)) goes from 1 to 0, therefore at a frequency of 512 Hz (regardless of whether double-speed is active).
 Thus, the counter can be made to increase faster by writing to `DIV` while its relevant bit is set (which clears `DIV`, and triggers the falling edge).
 
 The following events occur every <var>N</var> DIV-APU ticks:

src/CGB_Registers.md

@@ -28,6 +28,8 @@ use "repaired" color palette data matching for GBA displays.
 
 ### LCD VRAM DMA Transfers
 
+One of the pitfalls of the `HDMAx` naming convention is that the register's purpose is not immediately clear from its name, so some alternative `VDMA_*` names have been proposed, [such as `VDMA_LEN` for `HDMA5`](https://github.com/gbdev/hardware.inc/blob/8d4432e5796bffe2e13c438013285c5f11c37b99/hardware.inc#L919).
+
 #### FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): VRAM DMA source (high, low) \[write-only\]
 
 These two registers specify the address at which the transfer will read
@@ -142,7 +144,7 @@ corresponding Tile Maps.
 Reading from this register will return the number of the currently
 loaded VRAM bank in bit 0, and all other bits will be set to 1.
 
-### FF4D — KEY1 (CGB Mode only): Prepare speed switch
+### FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch
 
 {{#bits 8 >
    "KEY1" 7:"Current speed" 0:"Switch armed"
@@ -219,7 +221,7 @@ ON/OFF pulses (length 10us ON, 17.5us OFF each) instead of a permanent
 880us LED ON signal. Even though being generally CGB compatible, the GBA
 does not include an infra-red port.
 
-### FF4C — KEY0 (CGB Mode only): CPU mode select 
+### FF4C — KEY0/SYS (CGB Mode only): CPU mode select
 
 This GBC-only register (which is not officially documented) is written only by the CGB boot ROM,
 as it gets locked after the bootrom finish execution (by a write to the [BANK register](<#Monochrome models (DMG0, DMG, MGB)>)).
@@ -251,7 +253,7 @@ This register serves as a flag for which object priority mode to use. While
 the DMG prioritizes objects by x-coordinate, the CGB prioritizes them by
 location in OAM. This flag is set by the CGB bios after checking the game's CGB compatibility.
 
-OPRI has an effect if a [PGB](<#PGB mode>) value (`0xX8`, `0xXC`) is written to [KEY0](<#FF4C — KEY0 (CGB Mode only): CPU mode select>) but STOP hasn't been executed yet, and the write takes effect instantly.
+OPRI has an effect if a [PGB](<#PGB mode>) value (`0xX8`, `0xXC`) is written to [KEY0](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>) but STOP hasn't been executed yet, and the write takes effect instantly.
 
 :::warning TO BE VERIFIED
 
@@ -266,7 +268,7 @@ It is not known if triggering a PSM NMI, which remaps the boot ROM, has an effec
 
 - **Priority mode** (*Read/Write*): `0` = CGB-style priority, `1` = DMG-style priority
 
-### FF70 — SVBK (CGB Mode only): WRAM bank
+### FF70 — SVBK/WBK (CGB Mode only): WRAM bank
 
 In CGB Mode, 32 KiB of internal RAM are available.
 This memory is divided into 8 banks of 4 KiB each.

src/Hardware_Reg_List.md

@@ -45,8 +45,10 @@ $FF48      | [OBP0]      | OBJ palette 0 data
 $FF49      | [OBP1]      | OBJ palette 1 data                                                | R/W                 | DMG
 $FF4A      | [WY]        | Window Y position                                                 | R/W                 | All
 $FF4B      | [WX]        | Window X position plus 7                                          | R/W                 | All
-$FF4D      | [KEY1]      | Prepare speed switch                                              | Mixed               | CGB
+$FF4C      | [KEY0/SYS]  | CPU mode select                                                   | Mixed               | CGB
+$FF4D      | [KEY1/SPD]  | Prepare speed switch                                              | Mixed               | CGB
 $FF4F      | [VBK]       | VRAM bank                                                         | R/W                 | CGB
+$FF50      | [BANK]      | Boot ROM mapping control                                          | W                   | All
 $FF51      | [HDMA1]     | VRAM DMA source high                                              | W                   | CGB
 $FF52      | [HDMA2]     | VRAM DMA source low                                               | W                   | CGB
 $FF53      | [HDMA3]     | VRAM DMA destination high                                         | W                   | CGB
@@ -58,7 +60,7 @@ $FF69      | [BCPD/BGPD] | Background color palette data / Background palette da
 $FF6A      | [OCPS/OBPI] | OBJ color palette specification / OBJ palette index               | R/W                 | CGB
 $FF6B      | [OCPD/OBPD] | OBJ color palette data / OBJ palette data                         | R/W                 | CGB
 $FF6C      | [OPRI]      | Object priority mode                                              | R/W                 | CGB
-$FF70      | [SVBK]      | WRAM bank                                                         | R/W                 | CGB
+$FF70      | [SVBK/WBK]  | WRAM bank                                                         | R/W                 | CGB
 $FF76      | [PCM12]     | Audio digital outputs 1 & 2                                       | R                   | CGB
 $FF77      | [PCM34]     | Audio digital outputs 3 & 4                                       | R                   | CGB
 $FFFF      | [IE]        | Interrupt enable                                                  | R/W                 | All
@@ -105,8 +107,10 @@ $FFFF      | [IE]        | Interrupt enable
 [OBP1]: <#FF48–FF49 — OBP0, OBP1 (Non-CGB Mode only): OBJ palette 0, 1 data>
 [WY]: <#FF4A–FF4B — WY, WX: Window Y position, X position plus 7>
 [WX]: <#FF4A–FF4B — WY, WX: Window Y position, X position plus 7>
-[KEY1]: <#FF4D — KEY1 (CGB Mode only): Prepare speed switch>
+[KEY0/SYS]: <#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>
+[KEY1/SPD]: <#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>
 [VBK]: <#FF4F — VBK (CGB Mode only): VRAM bank>
+[BANK]: <#Power-Up Sequence>
 [HDMA1]: <#FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): VRAM DMA source (high, low) \[write-only\]>
 [HDMA2]: <#FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): VRAM DMA source (high, low) \[write-only\]>
 [HDMA3]: <#FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]>
@@ -118,7 +122,7 @@ $FFFF      | [IE]        | Interrupt enable
 [OCPS/OBPI]: <#FF6A–FF6B — OCPS/OBPI, OCPD/OBPD (CGB Mode only): OBJ color palette specification / OBJ palette index, OBJ color palette data / OBJ palette data>
 [OCPD/OBPD]: <#FF6A–FF6B — OCPS/OBPI, OCPD/OBPD (CGB Mode only): OBJ color palette specification / OBJ palette index, OBJ color palette data / OBJ palette data>
 [OPRI]: <#FF6C — OPRI (CGB Mode only): Object priority mode>
-[SVBK]: <#FF70 — SVBK (CGB Mode only): WRAM bank>
+[SVBK]: <#FF70 — SVBK/WBK (CGB Mode only): WRAM bank>
 [PCM12]: <#FF76 — PCM12 (CGB Mode only): Digital outputs 1 & 2 \[read-only\]>
 [PCM34]: <#FF77 — PCM34 (CGB Mode only): Digital outputs 3 & 4 \[read-only\]>
 [IE]: <#FFFF — IE: Interrupt enable>

src/Memory_Map.md

@@ -31,10 +31,10 @@ $FF10   |  $FF26  |       DMG      | [Audio](<#Audio Registers>)
 $FF30   |  $FF3F  |       DMG      | [Wave pattern](<#FF30–FF3F — Wave pattern RAM>)
 $FF40   |  $FF4B  |       DMG      | LCD [Control](<#FF40 — LCDC: LCD control>), [Status](<#FF41 — STAT: LCD status>), [Position, Scrolling](<#LCD Position and Scrolling>), and [Palettes](<#Palettes>)
 $FF4F   |         |       CGB      | [VRAM Bank Select](<#FF4F — VBK (CGB Mode only): VRAM bank>)
-$FF50   |         |       DMG      | Set to non-zero to disable boot ROM
+$FF50   |         |       DMG      | [Boot ROM mapping control](<#Power-Up Sequence>)
 $FF51   |  $FF55  |       CGB      | [VRAM DMA](<#LCD VRAM DMA Transfers>)
 $FF68   |  $FF6B  |       CGB      | [BG / OBJ Palettes](<#LCD Color Palettes (CGB only)>)
-$FF70   |         |       CGB      | [WRAM Bank Select](<#FF70 — SVBK (CGB Mode only): WRAM bank>)
+$FF70   |         |       CGB      | [WRAM Bank Select](<#FF70 — SVBK/WBK (CGB Mode only): WRAM bank>)
 
 ## VRAM memory map
 

src/Power_Up_Sequence.md

@@ -86,8 +86,8 @@ Then, like the monochrome boot ROMs, the header logo is checked *from the buffer
 For unknown reasons, however, only the first half of the logo is checked, despite the full logo being present in the HRAM buffer.
 
 Finally, the boot ROM fades all BG palettes to white, and sets the hardware to compatibility mode.
-If [the CGB compatibility byte](<#0143 — CGB flag>) indicates CGB compatibility, the byte is written directly to [`KEY0`](<#FF4C — KEY0 (CGB Mode only): CPU mode select>), potentially [enabling "PGB mode"](<#PGB mode>);
-otherwise, $04 is written to [`KEY0`](<#FF4C — KEY0 (CGB Mode only): CPU mode select>) (enabling DMG compatibility mode in the CPU),
+If [the CGB compatibility byte](<#0143 — CGB flag>) indicates CGB compatibility, the byte is written directly to [`KEY0`](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>), potentially [enabling "PGB mode"](<#PGB mode>);
+otherwise, $04 is written to [`KEY0`](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>) (enabling DMG compatibility mode in the CPU),
 $01 is written to [`OPRI`](<#FF6C — OPRI (CGB Mode only): Object priority mode>) (enabling [DMG OBJ priority](<#Object Priority and Conflicts>)), and the [compatibility palettes](<#Compatibility palettes>) are written.
 Additionally, the DMG logo tilemap is written [if the compatibility requests it](<#Compatibility palettes>).
 
@@ -314,8 +314,10 @@ Name          | Address | DMG0     | DMG / MGB | SGB / SGB2 | CGB / AGB
 [`OBP1`]      | $FF49   | ??[^obp] | ??[^obp]  | ??[^obp]   | ??[^obp]
 [`WY`]        | $FF4A   | $00      | $00       | $00        | $00
 [`WX`]        | $FF4B   | $00      | $00       | $00        | $00
+[`KEY0`]      | $FF4C   | ---      | ---       | ---        | ??[^unk]
 [`KEY1`]      | $FF4D   | ---      | ---       | ---        | $7E[^cgb_only]
 [`VBK`]       | $FF4F   | ---      | ---       | ---        | $FE[^cgb_only]
+[`BANK`]      | $FF50   | ---      | ---       | ---        | ---
 [`HDMA1`]     | $FF51   | ---      | ---       | ---        | $FF[^cgb_only]
 [`HDMA2`]     | $FF52   | ---      | ---       | ---        | $FF[^cgb_only]
 [`HDMA3`]     | $FF53   | ---      | ---       | ---        | $FF[^cgb_only]
@@ -390,8 +392,10 @@ The table above was obtained from Mooneye-GB tests [`acceptance/boot_hwio-dmg0`]
 [`OBP1`]: <#FF48–FF49 — OBP0, OBP1 (Non-CGB Mode only): OBJ palette 0, 1 data>
 [`WY`]: <#FF4A–FF4B — WY, WX: Window Y position, X position plus 7>
 [`WX`]: <#FF4A–FF4B — WY, WX: Window Y position, X position plus 7>
-[`KEY1`]: <#FF4D — KEY1 (CGB Mode only): Prepare speed switch>
+[`KEY0`]: <#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>
+[`KEY1`]: <#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>
 [`VBK`]: <#FF4F — VBK (CGB Mode only): VRAM bank>
+[`BANK`]: <#Power-Up Sequence>
 [`HDMA1`]: <#FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): VRAM DMA source (high, low) \[write-only\]>
 [`HDMA2`]: <#FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): VRAM DMA source (high, low) \[write-only\]>
 [`HDMA3`]: <#FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]>
@@ -403,11 +407,5 @@ The table above was obtained from Mooneye-GB tests [`acceptance/boot_hwio-dmg0`]
 [`OCPS`]: <#FF6A–FF6B — OCPS/OBPI, OCPD/OBPD (CGB Mode only): OBJ color palette specification / OBJ palette index, OBJ color palette data / OBJ palette data>
 [`OCPD`]: <#FF6A–FF6B — OCPS/OBPI, OCPD/OBPD (CGB Mode only): OBJ color palette specification / OBJ palette index, OBJ color palette data / OBJ palette data>
 [`OPRI`]: <#FF6C — OPRI (CGB Mode only): Object priority mode>
-[`SVBK`]: <#FF70 — SVBK (CGB Mode only): WRAM bank>
-[FF72]: <#FF72–FF73 — Bits 0–7 (CGB Mode only)>
-[FF73]: <#FF72–FF73 — Bits 0–7 (CGB Mode only)>
-[FF74]: <#FF74 — Bits 0-7 (CGB Mode only)>
-[FF75]: <#FF75 — Bits 0-6>
-[`PCM12`]: <#FF76 — PCM12: PCM amplitudes 1 & 2 \[read-only\]>
-[`PCM34`]: <#FF77 — PCM34: PCM amplitudes 3 & 4 \[read-only\]>
+[`SVBK`]: <#FF70 — SVBK/WBK (CGB Mode only): WRAM bank>
 [`IE`]: <#FFFF — IE: Interrupt enable>

src/Rendering.md

@@ -9,7 +9,7 @@ The main implication of this rendering process is the existence of **raster effe
 The most famous raster effect is modifying the [scrolling registers](<#LCD Position and Scrolling>) between scanlines to create a ["wavy" effect](https://gbdev.io/guides/deadcscroll#effects).
 
 A "**dot**" = one 2<sup>22</sup> Hz (≅ 4.194 MHz) time unit.
-Dots remain the same regardless of whether the CPU is in [Double Speed mode](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>), so there are 4 dots per Single Speed M-cycle, and 2 per Double Speed M-cycle.
+Dots remain the same regardless of whether the CPU is in [Double Speed mode](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>), so there are 4 dots per Single Speed M-cycle, and 2 per Double Speed M-cycle.
 
 :::tip NOTE
 

src/The_Cartridge_Header.md

@@ -56,7 +56,7 @@ Value | Meaning
 `$80` | The game supports CGB enhancements, but is backwards compatible with monochrome Game Boys
 `$C0` | The game works on CGB only (the hardware ignores bit 6, so this really functions the same as `$80`)
 
-Setting bit 7 will trigger a write of this register value to [KEY0 register](<#FF4C — KEY0 (CGB Mode only): CPU mode select>) which sets the CPU mode.
+Setting bit 7 will trigger a write of this register value to [KEY0 register](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>) which sets the CPU mode.
 
 ## 0144–0145 — New licensee code
 

src/Timer_and_Divider_Registers.md

@@ -15,7 +15,7 @@ This register is incremented at a rate of 16384Hz (\~16779Hz on SGB).
 Writing any value to this register resets it to $00.
 Additionally, this register is reset when executing the `stop` instruction, and
 only begins ticking again once `stop` mode ends. This also occurs during a
-[speed switch](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>).
+[speed switch](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>).
 (TODO: how is it affected by the wait after a speed switch?)
 
 Note: The divider is affected by CGB double speed mode, and will