The aim of this repository is to roughly compare the size of different components. This project is not thought to be taped out.
There is some overhead in addition to the component itself, as the inputs are generated by shift registers and the outputs are mutliplexed. This is due to the limited IO capabilities of the Tiny Tapeout.
| Utilisation % | Wire length (um) | Total cells (excluding fill and tap) | Detail report | |
|---|---|---|---|---|
| 6 bit | 4.52 | 1270 | 110 | Report |
| 8 bit | 5.92 | 1726 | 137 | Report |
| Utilisation % | Wire length (um) | Total cells (excluding fill and tap) | Detail report | |
|---|---|---|---|---|
| 6 bit | 12.1 | 3782 | 229 | Report |
| 8 bit | 21.51 | 7737 | 398 | Report |
| Utilisation % | Wire length (um) | Total cells (excluding fill and tap) | Detail report | |
|---|---|---|---|---|
| 6 bit | 18.76 | 6723 | 347 | Report |
| 8 bit | 30.56 | 11544 | 541 | Report |
TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.
To learn more and get started, visit https://tinytapeout.com.
Edit the info.yaml and uncomment the source_files and top_module properties, and change the value of language to "Verilog". Add your Verilog files to the src folder, and list them in the source_files property.
The GitHub action will automatically build the ASIC files using OpenLane.
Please see the instructions for:
- Submit your design to the next shuttle on the website. The closing date is November 4th.
- Edit this README and explain your design, how it works, and how to test it.
- Share your GDS on your social network of choice, tagging it #tinytapeout and linking Matt's profile:
- LinkedIn #tinytapeout matt-venn
- Mastodon #tinytapeout @matthewvenn
- Twitter #tinytapeout @matthewvenn