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Liu Yonggang
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Dec 12, 2022
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from amaranth import ClockDomain, Module | ||
from amaranth.cli import main | ||
from amaranth_boards.arty_a7 import ArtyA7_100Platform | ||
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from thing_block import ThingBlock | ||
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# Usage: python3 elaborate_main.py generate -t [v|il|cc] > thing.[v|il|cc] | ||
# ArtyA7_100Platform | ||
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if __name__ == "__main__": | ||
sync = ClockDomain() | ||
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block = ThingBlock() | ||
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m = Module() | ||
m.domains += sync | ||
m.submodules += block | ||
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main(m, ports=[sync.clk, sync.rst], platform=None """ArtyA7_100Platform""") |
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#include <backends/cxxrtl/cxxrtl.h> | ||
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#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \ | ||
defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL) | ||
#include <backends/cxxrtl/cxxrtl_capi.cc> | ||
#endif | ||
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#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL) | ||
#include <backends/cxxrtl/cxxrtl_vcd_capi.cc> | ||
#endif | ||
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using namespace cxxrtl_yosys; | ||
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namespace cxxrtl_design { | ||
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// \amaranth.hierarchy: top | ||
// \top: 1 | ||
// \generator: Amaranth | ||
struct p_top : public module { | ||
// \src: elaborate_main.py:9 | ||
/*input*/ value<1> p_rst; | ||
// \src: elaborate_main.py:9 | ||
/*input*/ value<1> p_clk; | ||
p_top() {} | ||
p_top(adopt, p_top other) {} | ||
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void reset() override { | ||
*this = p_top(adopt {}, std::move(*this)); | ||
} | ||
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bool eval() override; | ||
bool commit() override; | ||
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void debug_eval(); | ||
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void debug_info(debug_items &items, std::string path = "") override; | ||
}; // struct p_top | ||
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bool p_top::eval() { | ||
bool converged = true; | ||
return converged; | ||
} | ||
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bool p_top::commit() { | ||
bool changed = false; | ||
return changed; | ||
} | ||
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void p_top::debug_eval() { | ||
} | ||
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CXXRTL_EXTREMELY_COLD | ||
void p_top::debug_info(debug_items &items, std::string path) { | ||
assert(path.empty() || path[path.size() - 1] == ' '); | ||
items.add(path + "rst", debug_item(p_rst, 0, debug_item::INPUT|debug_item::UNDRIVEN)); | ||
items.add(path + "clk", debug_item(p_clk, 0, debug_item::INPUT|debug_item::UNDRIVEN)); | ||
} | ||
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} // namespace cxxrtl_design | ||
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extern "C" | ||
cxxrtl_toplevel cxxrtl_design_create() { | ||
return new _cxxrtl_toplevel { std::unique_ptr<cxxrtl_design::p_top>(new cxxrtl_design::p_top) }; | ||
} | ||
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attribute \generator "Amaranth" | ||
attribute \amaranth.hierarchy "top.U$$0" | ||
module \U$$0 | ||
wire width 1 $empty_module_filler | ||
end | ||
attribute \generator "Amaranth" | ||
attribute \top 1 | ||
attribute \amaranth.hierarchy "top" | ||
module \top | ||
attribute \src "elaborate_main.py:9" | ||
wire width 1 input 0 \clk | ||
attribute \src "elaborate_main.py:9" | ||
wire width 1 input 1 \rst | ||
cell \U$$0 \U$$0 | ||
end | ||
end | ||
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/* Generated by Amaranth Yosys 0.10.0 (PyPI ver 0.10.0.dev47, git sha1 dca8fb54a) */ | ||
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(* \amaranth.hierarchy = "top.U$$0" *) | ||
(* generator = "Amaranth" *) | ||
module \U$$0 (); | ||
wire \$empty_module_filler ; | ||
endmodule | ||
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(* \amaranth.hierarchy = "top" *) | ||
(* top = 1 *) | ||
(* generator = "Amaranth" *) | ||
module top(rst, clk); | ||
(* src = "elaborate_main.py:8" *) | ||
input clk; | ||
(* src = "elaborate_main.py:8" *) | ||
input rst; | ||
\U$$0 \U$$0 ( | ||
); | ||
endmodule | ||
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from amaranth import Elaboratable, Module | ||
from amaranth.build import Platform | ||
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class ThingBlock(Elaboratable): | ||
def __init__(self): | ||
pass | ||
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def elaborate(self, platform: Platform) -> Module: | ||
m = Module() | ||
return m |