ROM module is worked

src/alu.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from src.isa import *
+from .isa import *
 
 v_filename = "alu.v"
 #######################################

src/rom.py

@@ -4,7 +4,7 @@
 from amaranth_soc.memory import *
 from amaranth_soc.wishbone import *
 
-from src.isa import *
+from .isa import *
 
 ###############################################
 # ROM module
@@ -13,22 +13,32 @@
 class ROM(Elaboratable):
     def __init__(self, data):
         # Data storage
-        self.size = len(data) * 4
         self.data = Memory(width=32, depth=len(data), init=data)
         self.r = self.data.read_port()
         # Initalize Wishbone bus arbiter
+        self.size = len(data) * 4
         self.arb = Arbiter(addr_width=ceil(log2(self.size+1)), data_width=32)
         self.arb.bus.memory_map = MemoryMap(addr_width=self.arb.bus.addr_width, data_width=self.arb.bus.data_width, alignment=0)
+
+    def new_bus(self):
+        #Initial a new wishbone bus interface
+        bus = Interface(addr_width=self.arb.bus.addr_width, data_width=self.arb.bus.data_width)
+        bus.memory_map = MemoryMap(addr_width=bus.addr_width, data_width=bus.data_width, alignment=0)
+        self.arb.add(bus)
+
+        #DMA support
+        return bus
+
 
     def elaborate(self, platform):
         m = Module()
-        #m.submodules.arb = self.arb
-        #m.submodules.r = self.r
+        m.submodules.arb = self.arb
+        m.submodules.r = self.r
 
         rws = Signal(1, reset=0)
         m.d.sync += [
-                rws.eq(self.arb.bus.cyc), 
-                self.arb.bus.ack.eq(self.arb.bus.cyc & rws)
+        	rws.eq(self.arb.bus.cyc), 
+            self.arb.bus.ack.eq(self.arb.bus.cyc & rws)
         ]
 
         m.d.comb += self.r.addr.eq(self.arb.bus.adr >> 2)

test/test_rom.py

@@ -3,37 +3,36 @@
 ####################################
 from amaranth.sim import Simulator, Tick, Settle
 import sys, os
-sys.path.append(os.getcwd()+"/../")
+sys.path.append("..")
 
 from src.isa import *
 from src.rom import *
 
 p = 0
 f = 0
-def rom_ut(dut, address, expected):
+def rom_read_ut(rom, address, expected):
     global p, f
-    yield dut.arb.bus.adr.eq(address)
-    yield Tick()
+    yield rom.arb.bus.adr.eq(address)
     yield Tick()
     yield Tick()
     yield Settle()
 
-    actual = yield dut.arb.bus.dat_r
-    if hexs(expected) != hexs(actual):
+    actual = yield rom.arb.bus.dat_r
+    if expected != actual:
         f += 1
-        print("\033[31mFAIL:\033[0m %s (got: %s)" % (hexs(expected), hexs(actual)))
+        print("\033[31mFAIL:\033[0m ROM[0x%08X] = 0x%08X (got: 0x%08X)" % (address, expected, actual))
     else:
         p += 1
-        print( "\033[32mPASS:\033[0m %s = %s" % (hexs(expected), hexs(actual)))
+        print( "\033[32mPASS:\033[0m ROM[0x%08X] = 0x%08X" % (address, expected))
 
-def rom_test(dut):
+def rom_test(rom):
     yield Settle()
     print("---ROM Tests---")
-    yield dut.arb.bus.cyc.eq(1)
-    yield from rom_ut(dut, 0, 0x01234567)
-    yield from rom_ut(dut, 1, 0x89abcdef)
-    yield from rom_ut(dut, 2, 0x42424242)
-    yield from rom_ut(dut, 3, 0xdeadbeef)
+    yield rom.arb.bus.cyc.eq(1)
+    yield from rom_read_ut(rom, 0x0, little_end(0x01234567))
+    yield from rom_read_ut(rom, 0x4, little_end(0x89abcdef))
+    yield from rom_read_ut(rom, 0x8, little_end(0x42424242))
+    yield from rom_read_ut(rom, 0xc, little_end(0xdeadbeef))
 
     yield Tick()
     print("ROM Tests: %d Passed, %d Failed" % (p, f))