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try to repair full-speed clock
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glitchcore committed Nov 20, 2018
1 parent 3039067 commit 699c486
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion v/usb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ reg prev_clk_usb_data;
always@ (posedge clk) begin
prev_clk_usb_data <= in_usb_data;

if(prev_clk_usb_data ^ in_usb_data) usb_clk_cnt <= 5'd12;
if(prev_clk_usb_data ^ in_usb_data) usb_clk_cnt <= is_fs ? 5'd8 : 5'd12;
else usb_clk_cnt <= usb_clk_cnt + 5'd1;

// proxy_usb_data <= in_usb_data;
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