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Add Wishbone burst support to HPS NXLRAM interface #533

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Add Wishbone burst support to HPS NXLRAM interface #533

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Commits on May 9, 2022

  1. soc/hps*.py: Add Wishbone burst support to NXLRAM interface 

    This commit adds support for incrementing address burst cycles
in NXLRAM Wishbone interface.
Ported from enjoy-digital/litex#1267

Signed-off-by: Rafal Kolucki <[email protected]>
    @koluckirafal
    koluckirafal committed May 9, 2022
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