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Sub mee #303

Closed
wants to merge 115 commits into from
Closed

Sub mee #303

wants to merge 115 commits into from

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FarmerJooe
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gvoskuilen and others added 30 commits October 26, 2020 15:19
@gvoskuilen
Fix for bugs in lazy write handling
b7b9dc0
@mkhairy
Merge pull request gpgpu-sim#3 from gvoskuilen/dev
2d73b61 
Fix for bugs in lazy write handling
@allencho1222
change address type into ull
950464e
@allencho1222
do not truncate 32 MSB bits of the memory address
07f77e1
@JRPan
added MSHR_HIT
132c2ce
@mkhairy
Merge pull request gpgpu-sim#6 from JRPan/add_mshr
85e36b9 
added MSHR_HIT
@tgrogers
Merge pull request gpgpu-sim#4 from allencho1222/patch-1
29cce50 
change address type into ull
@tgrogers
Merge pull request gpgpu-sim#5 from allencho1222/patch-2
e6b0608 
do not truncate 32 MSB bits of the memory address
@mkhairy
Merge branch 'dev' of https://github.com/accel-sim/gpgpu-sim_distribu…
5ac0b60 
…tion into HEAD
@JRPan
bug fix was_writeback_sent
f3a0077
@mkhairy
Merge pull request gpgpu-sim#7 from JRPan/fix-was_writeback_sent
67f89ab 
bug fix was_writeback_sent()
@JRPan
fix hash funciton
51d9925
@mkhairy
Merge pull request gpgpu-sim#9 from JRPan/fix-cache-hash
2f96645 
Fix cache hash function and renaming
@mkhairy
adding new RTX 3070 config
b430b36
@mkhairy
Merge branch 'dev' of https://github.com/accel-sim/gpgpu-sim_distribu…
deb5eb5 
…tion into HEAD
@mkhairy
change the L1 cache policy to be on-miss based on recent ubench
09f10eb
@mkhairy
change the L1 cache policy based on recent ubench
1ee03f0
@barnes88
parition CU allocation, add prints
5533464
@barnes88
minor fixes
645a0ea
@barnes88
useful print statement
46423a2
@barnes88
validated collector unit partitioning based on scheduler
b672880
@barnes88
sub core model dispatches only to assigned exec pipelines
fa76ab4
@barnes88
minor fix accessing du
c905726
@barnes88
fix find_ready reg_id
a72b84e
@barnes88
dont need du id
6ad5bad
@barnes88
remove prints
9219236
@barnes88
need at least 1 cu per sched for sub_core model, fix find_ready() reg_id
52a890c
@barnes88
move reg_id calc to cu object init
2db9120
@barnes88
fix assert
4825a1d
@barnes88
clean up redundant method args
e2b410d
mkhairy and others added 28 commits May 19, 2021 22:20
@mkhairy
change L1 cache config in Volta+ to be write-through and write-alloca…
7fac247 
…te based on recent ubench
@mkhairy
oops delete this config, it should not be pushed
0d33266
@mkhairy
Merge pull request gpgpu-sim#16 from mkhairy/dev
2aef4e3 
Updating config files and code refactoring of Junuri's code
@JRPan
fix merge conflict
c8eca04
@JRPan
L2 breakdown - reuse mf allocator
f665ad5
@JRPan
cast to float - dirty line percentage
b814c52
@mkhairy
Merge pull request gpgpu-sim#17 from JRPan/rewrite-l2-breakdown
ce4f20f 
Rewrite l2 breakdown
@mkhairy
Update version
3b75d8f
@mkhairy
Update CHANGES
7e48560
@mkhairy
Update README.md
b6409b4
@mkhairy
format code
6c9e13d
@mkhairy
updating the configs based on the tuner output
778962e
@mkhairy
changing kernel latency
3eea014
@mkhairy
fixing configs
6ad461a
@JRPan
rewrite shmem_option parsing
110aeb1
@JRPan
update readable
04462cb
@JRPan
minor improvements
e9d781a
@JRPan
correct dirty counter
0f088dc
@JRPan
WT in lazy fetch on read
3cf24b8
@JRPan
Adding restricted round robin scheduler
b1befa8
@JRPan
better oc selecting when sub core enabled
b658147
@JRPan
Update volta to use lrr scheduler
a8256e5
@JRPan
Ampere and Turing also lrr scheduler
84c4f46
@VijayKandiah
Merge pull request gpgpu-sim#5 from accel-sim/dev
4a4fc87 
GPGPU-Sim Latest Dev Integration
@VijayKandiah
AccelWattch dev Integration
84c6cf4
@aamodt
Merge pull request gpgpu-sim#236 from accel-sim/dev
da0aef2 
Update to latest accel-sim:dev
@aamodt
Merge pull request gpgpu-sim#237 from VijayKandiah/dev
6b244a5 
AccelWattch v1.0 Integration into Dev
@FarmerJooe
mee sub partition v0.1
f9b39ee
@tgrogers
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Looks like internal work.
If this is relevant to the mainline, please create a new PR.

@tgrogers tgrogers closed this Feb 11, 2025
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9 participants
@FarmerJooe @tgrogers @gvoskuilen @mkhairy @allencho1222 @JRPan @barnes88 @VijayKandiah @aamodt