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A RISC-V 5 stage in-order pipeline processer capable of booting RT-Thread , XV6 and Linux operating system

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happy-lx/simplecore

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一生一芯项目

支持RV64IMAZicsr指令集,实现M/S/U模式,实现TLB和Cache,实现两位饱和计数器的分支预测

git clone https://github.com/happy-lx/simplecore.git
make file=final
cd tool/elf && make install depth=16384 file=file_you_want_to_test
cd ../../src/test/scala/gcd/utest/ && bash make.sh
cd obj_dir && ./Vtop

开发进程见log.md

设计文档见doc/

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A RISC-V 5 stage in-order pipeline processer capable of booting RT-Thread , XV6 and Linux operating system

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