[DCD_DWC2][ESP32P4][HS] Added cache synchronization #2877
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
roma-jam
changed the title
roma-jam
changed the title
roma-jam
changed the title
roma-jam
changed the title
roma-jam
force-pushed
the
feature/esp32p4_dma_cache_syncronization
branch
from
3235722
to
a88dd32
Compare
roma-jam
force-pushed
the
feature/esp32p4_dma_cache_syncronization
branch
from
a88dd32
to
2a56780
Compare
roma-jam
commented
Nov 14, 2024
|
this is great, give me a bit of time, I am currently in the middle of refactoring dcd dwc2 https://github.com/hathach/tinyusb/tree/enhance-dwc2-dcd though we should name it dcd_dcache_clean/invalidate() https://github.com/hathach/tinyusb/blob/enhance-dwc2-dcd/src/device/dcd.h#L96 as other ports. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Requirements
On ESP32P4 it is important to synchronize cache and memory during DMA transactions.
To use the DMA feature the following should be done:
.dram1Thus, the values
CFG_TUSB_MEM_SECTIONandCFG_TUSB_MEM_ALIGNshould be provided, according to the target chip.Description
Added cache synchronization macroses during
xferpreparation/completion:dsync_c2m(_addr, _size)- Synchronizing cache to memorydsync_m2c(_addr, _size)- Synchronizing memory to cacheRelated