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📝 chisel + verilator #60

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merged 18 commits into from
May 27, 2024
2 changes: 1 addition & 1 deletion docs/guide-for-beginner/git-tutorial.md
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Expand Up @@ -38,7 +38,7 @@ Git 的管理是基于仓库(Repository)的,仓库可以看成一个储存
- 暂存区(Staging Area):即我们的缓存区,我们可以通过 `git add` 命令将工作区的文件(或文件的变动)添加到暂存区。暂存区存储了我们对文件的修改。
- 仓库(Repository):即我们的版本库,我们可以通过 `git commit` 命令将暂存区的文件提交到仓库。

值得注意的是,由于我们对文件的编辑都发生在工作目录下,所以我们增删文件或对文件进行修改,都只会影响工作区,而不会影响暂存区和仓库。所以我们可以很容易地撤销在工作区发生的修改,这也是 Git 的优势之一。 我们真正想要在仓库中修改一个文件,实际上需要经历三个步骤:
值得注意的是,由于我们对文件的编辑都发生在工作目录下,所以我们增删文件或对文件进行修改,都只会影响工作区,而不会影响暂存区和仓库。所以我们可以很容易地撤销在工作区发生的修改,这也是 Git 的优势之一。我们真正想要在仓库中修改一个文件,实际上需要经历三个步骤:

1. 在工作目录中修改文件。
2. 使用 `git add` 将修改的文件添加到暂存区。
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2 changes: 1 addition & 1 deletion docs/popular-science/bash-dlc.md
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Expand Up @@ -91,7 +91,7 @@ $ echo a{d,c,b}e
ade ace abe
```

大括号内还可以写数字/字符+增长,比如 `{x..y[..incr]}`
大括号内还可以写数字/字符 + 增长,比如 `{x..y[..incr]}`
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大括号展开是严格 "词法" 的,它不会对任何特殊字符作出 "反应", 包括大括号自己:

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127 changes: 127 additions & 0 deletions docs/unofficial-lab-env/comp-organ-lab2.md
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# 计算机组成原理实验 2 环境指南(非官方)

以下指南适合有 linux 环境的同学使用。

笔者心态:对 verilog 感到不适,并且想折腾一些花样。
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Verilog


## 实验需要的工具

- verilator
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Verilator

- chisel
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Chisel

- gtkwave
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GTKWave


## 安装依赖

实验工具安装需要
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使用规范的商标/产品名,并且不鼓励使用每一项都很短且整体很长的 bullet list


- bison
- flex
- gcc
- git
- g++
- java
- make
- sbt
- scala
- sdkman
- verilator

通过以下命令可以安装

```sh
# Debian
sudo apt install build-essential git device-tree-compiler
# Ubuntu
sudo apt install build-essential git device-tree-compiler
# ArchLinux
sudo pacman -Sy base-devel git dtc
# opensuse
sudo zypper in -t pattern devel_C_C++
```

如果配置环境过程中出现“command not found.”可能是有依赖的工具没装,此时可以利用搜索引擎。
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现 “command not found.” 可


## 安装 bison 和 flex

bison 和 flex 是 gnu 提供的两个语法解析工具。
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GNU

(verilator 依赖这两个工具将 verilog 代码编译成 c++ 的 class)

```sh
#opensuse
sudo zypper in bison flex
```

## 安装 verilator
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```sh
# 先 cd 到一个文件夹中,推荐 cd 到 ~/Downloads
git clone https://github.com/verilator/verilator
cd verilator
autoconf # Create ./configure script
./configure # Configure and create Makefile
make -j `nproc` # Build Verilator itself (if error, try just 'make')
sudo make install # 这会安装到 /usr 中
```

如果需要一些个性化,比方说安装到非`/usr`目录,或者想要其他支持,请查阅 verilator 的安装文档 https://verilator.org/guide/latest/install.html#git-quick-install

( 因为 verilator 在编译的时候,需要使用 gnu 方言,因此推荐使用 linux )

## 安装 sdkman

```sh
curl -s "https://get.sdkman.io" | bash
```

安装过程中,注意看提示

## 安装 java

```sh
sdk install java
```

## 安装 scala 2.12.13

```sh
sdk install scala 2.12.13
```

## 安装 gtkwave

```sh
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# opensuse
sudo zypper in gtkwave
# windows
winget install gtkwave
# mac
brew install gtkwave
```

如果 windows/mac 作为宿主系统,应该是在 windows/mac 中安装 gtkwave,然后在 windows 打开 `.vcd` 文件。

但是 mac 实际上使用 gtkwave 会有点问题(无法双击打开)。但是可以在 shell 中 `gtkwave <.vcd>`打开。

如果是 ssh 连接的 linux,可以使用 CyberDuck 或者是 MountainDuck(付费)或者是 sshfs 挂载目录,然后在 宿主机上 `gtkwave <.vcd>` 或者是双击打开。(笔者就是用的这种方式)
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说起来, 之前 @rewired-gh 教过我一个东西: 如何让 gtkwave 打开的时候把所有信号都展示出来. 原理大概是写一个 tcl 脚本来调 gtkwave:

# add_all_and_zoom_full.tcl
# Add all signals
set nfacs [ gtkwave::getNumFacs ]
set all_facs [list]
for {set i 0} {$i < $nfacs } {incr i} {
  set facname [ gtkwave::getFacName $i ]
  lappend all_facs "$facname"
}
set num_added [ gtkwave::addSignalsFromList $all_facs ]
puts "num signals added: $num_added"

# Zoom full
gtkwave::/Time/Zoom/Zoom_Full

# Print
# set dumpname [ gtkwave::getDumpFileName ]
# gtkwave::/File/Print_To_File PDF {Letter (8.5" x 11")} Minimal $dumpname.pdf

然后:

gtkwave -S add_all_and_zoom_full.tcl <.vcd> 2> /dev/null

有需要的话可以加上这一段.


## 创建 chisel 项目

chisel 是 scala 的一个库并且目前为止并没有一个真正的 chisel IDE。我们可以通过官方的 chisel-template 创建我们的项目。

```sh
git clone https://github.com/chipsalliance/chisel-template.git <my-chisel-project>
```

然后在 vscode 中打开我们的 chisel 就行了。当然也可以用其他的 IDE (neovim is the best ide in the world!)
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## 调试 chisel 生成的 verilog
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可以使用 C++ 和 verilator 调试我们的 module。

这是 verilator 的使用教程:https://itsembedded.com/dhd_list/

## 使用 gtkwave 打开波形仿真文件

```sh
gtkwave mul.vcd
```
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