Indigo Alpha2
Pre-release
Pre-release
This is an alpha release of the PiTubeDirect Indigo version.
IMPORTANT: If you want to use RISC-V BBC Basic on the RISC-V Co Processor, you must use version 20230910 or later, available here.
Changes from Indigo Alpha1 include:
Tube ULA:
- 4328a11 tube-ula.c : Fix software reset using bit 5 bug #63
- 3029fc8 Tube ULA: Fix two byte data transfer flags incorrect (#179)
Co Pro 15 (Native ARM Co Pro)
- 73491aa Darm.c : improve ldr/str rd,[PC,#xx] output
- 00606e8 Frame Buffer: POINT's offscreen check is not right (#175)
Co Pro 23 (RISC-V Co Pro):
- 3029fc8 Tube ULA: Fix two byte data transfer flags incorrect (#179)
- b3acee4 Co Pro RISC-V: fix type 3 data transfer used by Econet ANFS (#178)
- 9e42159 Co Pro RISC-V: Update OSFILE and OSGBPB APIs to use individual registers (#180, #181)
- cd6e516 Co Pro RISC-V: Make ECALL_BASE a symbol
- ee13dca Co Pro RISC-V: Update ECALL_BASE to 0x00AC0000 (#183)
- a6bb664 Co Pro RISC-V: Implement UnknownEcallHandler vector (#185)
- b8ce64e Co Pro RISC-V: Implement Uncaught Exception Handler (#184)
- f1b0383 Co Pro RISC-V: Seperate out workspace (RAM) from program (ROM)
- 5b2601a Co Pro RISC-V: Implement Current Program and OS_SYSCTRL a0=1 (#182)
- 3852dd0 Co Pro RISC-V: Fix wrong syscall number in *PI command
- bbbb816 Co Pro RISC-V: Use stack for tmp buffers in OSARGS and *PI
- 37e4c36 Co Pro RISC-V: Move ECALL table into RAM and implement OS_HANDLERS with a0>=0
- 28d97db Co Pro RISC-V: *HELP shows correct version
- 8cc21c2 Co Pro RISC-V: Default uncaught exception handler dumps all registers (#186)
- e18a5fa Co Pro RISC-V: Show accurate SP in register dump
- 47faff9 Co Pro RISC-V: Small improvement to OS_HANDLERS
Co Pro 24 (JIT 6502 Co Pro):
- 54ac16c jit.s typo and speed up stz