Add phase testing capability to DRAMsim3

.gitattributes

@@ -0,0 +1,3 @@
+* text=auto eol=lf
+*.{cmd,[cC][mM][dD]} text eol=crlf
+*.{bat,[bB][aA][tT]} text eol=crlf

.gitignore

@@ -46,3 +46,16 @@ release
 
 # IDEs / Editors
 .vscode/
+
+# Temporary traces
+dramsim3.json
+dramsim3.txt
+
+# CMake stuff
+CMakeCache.txt
+CMakeFiles/
+cmake_install.cmake
+Makefile
+
+# DS_Store
+.DS_Store

.vscode/tasks.json

@@ -1,12 +1,27 @@
 {
     // See https://go.microsoft.com/fwlink/?LinkId=733558
     // for the documentation about the tasks.json format
-    "version": "0.1.0",
+    "version": "2.0.0",
     "command": "make",
-    "isShellCommand": true,
-    "args": ["-j5"],
-    "showOutput": "always",
+    "args": [
+        "-j5"
+    ],
     "options": {
         "cwd": "${workspaceRoot}/build"
-    }
+    },
+    "tasks": [
+        {
+            "label": "make",
+            "type": "shell",
+            "command": "make",
+            "args": [
+                "-j5"
+            ],
+            "problemMatcher": [],
+            "group": {
+                "_id": "build",
+                "isDefault": false
+            }
+        }
+    ]
 }

CMakeLists.txt

@@ -39,6 +39,8 @@ add_library(dramsim3 SHARED
     src/simple_stats.cc
     src/timing.cc
     src/memory_system.cc
+    src/phase_stats.cc
+    src/phase_detector.cc
 )
 
 if (THERMAL)
@@ -67,6 +69,10 @@ if (THERMAL)
     target_compile_options(thermalreplay PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS})
 endif (THERMAL)
 
+if (PHASEANALYSIS)
+    target_compile_options(dramsim3 PRIVATE -DPHASEANALYSIS)
+endif (PHASEANALYSIS)
+
 if (CMD_TRACE)
     target_compile_options(dramsim3 PRIVATE -DCMD_TRACE)
 endif (CMD_TRACE)

Dockerfile

@@ -0,0 +1,8 @@
+FROM ubuntu:20.04
+
+WORKDIR ../DRAMSIM3
+
+RUN  apt-get update \
+  && apt-get install -y make \
+  && apt-get install -y cmake \
+  && apt-get install -y build-essential

configs_custom/DDR3_8Gb_x16_1866_ideal.ini

@@ -0,0 +1,68 @@
+[dram_structure]
+protocol = IDEAL
+bankgroups = 1
+banks_per_group = 8
+rows = 65536
+columns = 1024
+device_width = 16
+BL = 8
+
+[timing]
+tCK = 1.07
+AL = 0
+CL = 13
+CWL = 9
+tRCD = 13
+tRP = 13
+tRAS = 32
+tRFC = 328
+tRFC2 = 328
+tRFC4 = 328
+REFI = 7290
+tRPRE = 0
+tWPRE = 0
+tRRD_S = 6
+tRRD_L = 
+tWTR_S = 7
+tWTR_L = 7
+tFAW = 33
+tWR = 15
+tWR2 = 15
+tRTP = 7
+tCCD_S = 4
+tCCD_L = 4
+tCKE = 5
+tCKESR = 6
+tXS = 338
+tXP = 6
+tRTRS = 1
+ideal_memory_latency = 20
+
+[power]
+VDD = 1.35
+IDD0 = 69
+IPP0 = 0.0
+IDD2P = 11
+IDD2N = 38
+IDD3P = 38
+IDD3N = 53
+IDD4W = 195
+IDD4R = 195
+IDD5AB = 275
+IDD6x = 24
+
+[system]
+channel_size = 8192
+channels = 1
+bus_width = 64
+address_mapping = rochrababgco
+queue_structure = PER_BANK
+refresh_policy = RANK_LEVEL_STAGGERED
+row_buf_policy = OPEN_PAGE
+cmd_queue_size = 8
+trans_queue_size = 32
+
+[other]
+epoch_period = 934579
+output_level = 1
+

configs_custom/DDR3_8Gb_x16_1866_large_transaction_queue.ini

@@ -0,0 +1,68 @@
+[dram_structure]
+protocol = MODEL_SWAP
+bankgroups = 1
+banks_per_group = 8
+rows = 65536
+columns = 1024
+device_width = 16
+BL = 8
+
+[timing]
+tCK = 1.07
+AL = 0
+CL = 13
+CWL = 9
+tRCD = 13
+tRP = 13
+tRAS = 32
+tRFC = 328
+tRFC2 = 328
+tRFC4 = 328
+REFI = 7290
+tRPRE = 0
+tWPRE = 0
+tRRD_S = 6
+tRRD_L = 
+tWTR_S = 7
+tWTR_L = 7
+tFAW = 33
+tWR = 15
+tWR2 = 15
+tRTP = 7
+tCCD_S = 4
+tCCD_L = 4
+tCKE = 5
+tCKESR = 6
+tXS = 338
+tXP = 6
+tRTRS = 1
+ideal_memory_latency = 20
+
+[power]
+VDD = 1.35
+IDD0 = 69
+IPP0 = 0.0
+IDD2P = 11
+IDD2N = 38
+IDD3P = 38
+IDD3N = 53
+IDD4W = 195
+IDD4R = 195
+IDD5AB = 275
+IDD6x = 24
+
+[system]
+channel_size = 8192
+channels = 1
+bus_width = 64
+address_mapping = rochrababgco
+queue_structure = PER_BANK
+refresh_policy = RANK_LEVEL_STAGGERED
+row_buf_policy = OPEN_PAGE
+cmd_queue_size = 8
+trans_queue_size = 1024
+
+[other]
+epoch_period = 934579
+output_level = 1
+

configs_custom/DDR3_8Gb_x16_1866_model_swap.ini

@@ -0,0 +1,68 @@
+[dram_structure]
+protocol = MODEL_SWAP
+bankgroups = 1
+banks_per_group = 8
+rows = 65536
+columns = 1024
+device_width = 16
+BL = 8
+
+[timing]
+tCK = 1.07
+AL = 0
+CL = 13
+CWL = 9
+tRCD = 13
+tRP = 13
+tRAS = 32
+tRFC = 328
+tRFC2 = 328
+tRFC4 = 328
+REFI = 7290
+tRPRE = 0
+tWPRE = 0
+tRRD_S = 6
+tRRD_L = 
+tWTR_S = 7
+tWTR_L = 7
+tFAW = 33
+tWR = 15
+tWR2 = 15
+tRTP = 7
+tCCD_S = 4
+tCCD_L = 4
+tCKE = 5
+tCKESR = 6
+tXS = 338
+tXP = 6
+tRTRS = 1
+ideal_memory_latency = 20
+
+[power]
+VDD = 1.35
+IDD0 = 69
+IPP0 = 0.0
+IDD2P = 11
+IDD2N = 38
+IDD3P = 38
+IDD3N = 53
+IDD4W = 195
+IDD4R = 195
+IDD5AB = 275
+IDD6x = 24
+
+[system]
+channel_size = 8192
+channels = 1
+bus_width = 64
+address_mapping = rochrababgco
+queue_structure = PER_BANK
+refresh_policy = RANK_LEVEL_STAGGERED
+row_buf_policy = OPEN_PAGE
+cmd_queue_size = 8
+trans_queue_size = 32
+
+[other]
+epoch_period = 934579
+output_level = 1
+