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1. AHB_GEN_201 AHB_GEN_201 Public

   An AHP Bus Generator From my Thesis Proposal in HCMUT

   SystemVerilog

2. SPI_APB SPI_APB Public

   A SPI design (supporting APB interfaces) using Systemverilog from VG_CPU project

   SystemVerilog 1 1

3. AXI4_BUS AXI4_BUS Public

   An AXI Bus Design - a part from Vanguard SoC project

   1