adding .project files for ppl and stix, ignoring all others

i4Ds · Jan 25, 2018 · 495765d · 495765d
1 parent c85076c
commit 495765d
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Showing 3 changed files with 40 additions and 3 deletions.
diff --git a/.gitignore b/.gitignore
@@ -2,9 +2,12 @@
 .metadata
 
 # ignore personal startup files
-startup_stix_sswidl*.bat
-stix_personal_startup*.pro
-**/.project
+startup_stix_sswidl*
+stix_personal_startup*
+dev/.project
+iunit/.project
+lldp/**/.project
+
 
 # ignore the fpga data folder
 fpga

diff --git a/ppl/.project b/ppl/.project
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ppl</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.rsi.idldt.core.IDLBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.rsi.idldt.core.IDLNature</nature>
+	</natures>
+</projectDescription>
diff --git a/stix/.project b/stix/.project
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>stix</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.rsi.idldt.core.IDLBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.rsi.idldt.core.IDLNature</nature>
+	</natures>
+</projectDescription>