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FIX: make arbiter not lazy
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iansseijelly committed Jan 28, 2025
1 parent 96f9850 commit 8db9f45
Showing 2 changed files with 27 additions and 31 deletions.
18 changes: 9 additions & 9 deletions src/main/scala/tile/RocketTile.scala
Original file line number Diff line number Diff line change
@@ -107,11 +107,6 @@ class RocketTile private(
case None => (Nil, Nil)
}

val trace_sink_arbiter = rocketParams.traceParams.map { t =>
val arb = LazyModule(new TraceSinkArbiter(traceSinkIds, use_monitor = t.useArbiterMonitor, monitor_name = rocketParams.uniqueName))
arb
}

val tile_master_blocker =
tileParams.blockerCtrlAddr
.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
@@ -182,15 +177,20 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
// reset vector is connected in the Frontend to s2_pc
core.io.reset_vector := DontCare

val trace_sink_arbiter = outer.rocketParams.traceParams.map { t =>
val arb = Module(new TraceSinkArbiter(outer.traceSinkIds, use_monitor = t.useArbiterMonitor, monitor_name = outer.rocketParams.uniqueName))
arb
}

if (outer.rocketParams.traceParams.isDefined) {
core.io.trace_core_ingress.get <> outer.trace_encoder.get.module.io.in
outer.trace_encoder_controller.foreach { lm =>
outer.trace_encoder.get.module.io.control <> lm.module.io.control
}

outer.trace_sink_arbiter.foreach { lm =>
lm.module.io.target := outer.trace_encoder.get.module.io.control.target
lm.module.io.in <> outer.trace_encoder.get.module.io.out
trace_sink_arbiter.foreach { arb =>
arb.io.target := outer.trace_encoder.get.module.io.control.target
arb.io.in <> outer.trace_encoder.get.module.io.out
}

core.io.traceStall := outer.traceAuxSinkNode.bundle.stall || outer.trace_encoder.get.module.io.stall
@@ -200,7 +200,7 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)

outer.trace_sinks.zip(outer.traceSinkIds).foreach { case (sink, id) =>
val index = outer.traceSinkIds.indexOf(id)
sink.module.io.trace_in <> outer.trace_sink_arbiter.get.module.io.out(index)
sink.module.io.trace_in <> trace_sink_arbiter.get.io.out(index)
}

// Report unrecoverable error conditions; for now the only cause is cache ECC errors
40 changes: 18 additions & 22 deletions src/main/scala/trace/TraceSinkArbiter.scala
Original file line number Diff line number Diff line change
@@ -12,28 +12,24 @@ import freechips.rocketchip.resources.{SimpleDevice}
import freechips.rocketchip.tile._
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}

class TraceSinkArbiter(nSeq : Seq[Int], use_monitor: Boolean = false, monitor_name: String = "unknown")(implicit p: Parameters) extends LazyModule {
override lazy val module = new TraceSinkArbiterModuleImp(this)
override def shouldBeInlined = false
class TraceSinkArbiterModuleImp(outer: TraceSinkArbiter) extends LazyModuleImp(outer) {
val io = IO(new Bundle {
val target = Input(UInt(TraceSinkTarget.width.W))
val in = Flipped(Decoupled(UInt(8.W)))
val out = Vec(nSeq.size, Decoupled(UInt(8.W)))
})
val nVec = VecInit(nSeq.map(_.U))
io.in.ready := Mux(nVec.contains(io.target), io.out(nVec.indexWhere(_ === io.target)).ready, true.B)
io.out.zipWithIndex.foreach { case (o, i) =>
o.valid := io.in.valid && (io.target === nVec(i))
o.bits := io.in.bits
}
class TraceSinkArbiter(nSeq : Seq[Int], use_monitor: Boolean = false, monitor_name: String = "unknown") extends Module {
val io = IO(new Bundle {
val target = Input(UInt(TraceSinkTarget.width.W))
val in = Flipped(Decoupled(UInt(8.W)))
val out = Vec(nSeq.size, Decoupled(UInt(8.W)))
})
val nVec = VecInit(nSeq.map(_.U))
io.in.ready := Mux(nVec.contains(io.target), io.out(nVec.indexWhere(_ === io.target)).ready, true.B)
io.out.zipWithIndex.foreach { case (o, i) =>
o.valid := io.in.valid && (io.target === nVec(i))
o.bits := io.in.bits
}

if (use_monitor) {
val monitor = Module(new TraceSinkMonitor(s"trace_monitor_$monitor_name.out"))
monitor.io.in_fire := io.in.valid && io.in.ready
monitor.io.in_byte := io.in.bits
monitor.io.clk := clock
monitor.io.reset := reset
}
if (use_monitor) {
val monitor = Module(new TraceSinkMonitor(s"trace_monitor_$monitor_name.out"))
monitor.io.in_fire := io.in.valid && io.in.ready
monitor.io.in_byte := io.in.bits
monitor.io.clk := clock
monitor.io.reset := reset
}
}

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