Mark bit ranges of swizzles with comments in generated SystemVerilog #627
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Description & Motivation
This PR introduces range comments on swizzles to make it easier to read the generated SystemVerilog. This seems a little more verbose and forces multi-line for swizzles whereas before this change it is possible to have a single line swizzle. However, the readability improvements for larger swizzles make this change worth it, I think.
Questions considered:
/* */style block comments instead of//so that it could still be in one line?SystemVerilogSynthesizer) instead of always on?An example of what it looks like (currently, post-formatting with verible):
Related Issue(s)
Fix #551
Testing
Added a bunch of new tests, and updated older tests to be able to still check against older format
Backwards-compatibility
No, but SV will change
Documentation
No