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@mkorbel1 mkorbel1 commented Oct 22, 2025

Description & Motivation

This PR introduces range comments on swizzles to make it easier to read the generated SystemVerilog. This seems a little more verbose and forces multi-line for swizzles whereas before this change it is possible to have a single line swizzle. However, the readability improvements for larger swizzles make this change worth it, I think.

Questions considered:

  • If the number of things swizzled is small (less than 3?) then maybe don't do this?
    • No, just do it for everything > 1, even when there are 2 elements it can be nice to see the range
  • Is this too difficult to read without formatting?
    • It doesn't really make things much harder to read in places where formatting wasn't already desireable.
  • Should we use /* */ style block comments instead of // so that it could still be in one line?
    • Yes! This avoids any potential issues with inlining.
  • Should this be a configurable flag (I guess in SystemVerilogSynthesizer) instead of always on?
    • Doing so now would probably add a decent amount of complexity to the whole system of Synthesizers, and probably be a breaking change, so we'll come back to it another time. In general, it's nicer to just have a good setting.

An example of what it looks like (currently, post-formatting with verible):

module SwizzleVariety (
    input  logic [ 7:0] a,
    output logic [34:0] b
);
  logic [3:0] x;
  logic [2:0][1:0] y;
  assign b = {
    1'h0,  /*    34 */
    a,  /* 33:26 */
    x,  /* 25:22 */
    ({
      y[2],  /* 5:4 */
      y[1],  /* 3:2 */
      y[0]  /* 1:0 */
    }),  /* 21:16 */
    5'h3,  /* 15:11 */
    ({
      3'h2,  /* 10:8 */
      a  /*  7:0 */
    })  /* 10: 0 */
  };  // swizzle
endmodule : SwizzleVariety

Related Issue(s)

Fix #551

Testing

Added a bunch of new tests, and updated older tests to be able to still check against older format

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No, but SV will change

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

@mkorbel1 mkorbel1 marked this pull request as ready for review November 5, 2025 20:27
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Mark bit ranges in swizzles in generated SystemVerilog

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