SPI FPGA v1.1

• Changed license to The MIT License.
• Added better simulations and enabled GitHub CI.
• Added Spirit Level example design for CYC1000 board.
• Added sync FFs to SPI slave for elimination metastability.
• Added WORD_SIZE generic.
• Many minor changes, fixes and optimizations.

Release v1.0

Release v1.0:

• added new version of master module with many optimalizations
• added DIN_LAST input to master module, for signal control CS_N
• added simulation tcl script for ModelSim
• updated simulation testbench
• updated example design
• optimized and cleaned slave module

Beta 2 release:

Beta 2 release:

• added SPI slave controller
• added example design for EP4CE6 Starter Board
• updated simulation testbench file

Beta release

Beta release:

• first implementation of SPI master controller
• not tested in hardware, only simulated
• no SPI slave controller