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6 changes: 3 additions & 3 deletions j1a/verilator/j1a.v
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ module j1a(input wire clk,
/* verilator lint_off UNUSED */
wire [12:0] code_addr;
/* verilator lint_on UNUSED */
wire [15:0] insn;
reg [15:0] insn;

reg [15:0] ram_prog[0:4095] /* verilator public_flat */;
always @(posedge clk) begin
Expand Down Expand Up @@ -57,8 +57,8 @@ module j1a(input wire clk,

// ###### UART ##########################################

wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
assign uart0_wr = io_wr_ & io_addr_[12];
assign uart0_rd = io_rd_ & io_addr_[12];
assign uart_w = dout_[7:0];

// always @(posedge clk) begin
Expand Down
3 changes: 2 additions & 1 deletion j1a/verilator/sim_main.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
#include <stdio.h>
#include "Vj1a.h"
#include "Vj1a___024root.h"
#include "verilated_vcd_c.h"

int main(int argc, char **argv)
Expand All @@ -20,7 +21,7 @@ int main(int argc, char **argv)
fprintf(stderr, "invalid hex value at line %d\n", i + 1);
exit(1);
}
top->v__DOT__ram_prog[i] = v;
top->rootp->v__DOT__ram_prog[i] = v;
}

top->resetq = 0;
Expand Down
13 changes: 7 additions & 6 deletions j1a/verilator/vsim.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
#include <assert.h>
#include "Vj1a.h"
#include "Vj1a___024root.h"
#include "verilated.h"
#define VCD 0
#if VCD
Expand Down Expand Up @@ -60,7 +61,7 @@ Vj1a_init(v3 *self, PyObject *args, PyObject *kwds)
fprintf(stderr, "invalid hex value at line %d\n", i + 1);
exit(1);
}
self->dut->v__DOT__ram_prog[i] = v;
self->dut->rootp->v__DOT__ram_prog[i] = v;
}
memset(self->rdepth, 0, sizeof(self->rdepth));
memset(self->ddepth, 0, sizeof(self->ddepth));
Expand Down Expand Up @@ -126,11 +127,11 @@ static void cycle(v3* v)
dut->clk = 1;
dut->eval();

int pc = 4095 & dut->v__DOT___j1__DOT__pc;
if (dut->v__DOT___j1__DOT__dstack__DOT__depth > v->ddepth[pc])
v->ddepth[pc] = dut->v__DOT___j1__DOT__dstack__DOT__depth;
if (dut->v__DOT___j1__DOT__rstack__DOT__depth > v->rdepth[pc])
v->rdepth[pc] = dut->v__DOT___j1__DOT__rstack__DOT__depth;
int pc = 4095 & dut->rootp->v__DOT___j1__DOT__pc;
if (dut->rootp->v__DOT___j1__DOT__dstack__DOT__depth > v->ddepth[pc])
v->ddepth[pc] = dut->rootp->v__DOT___j1__DOT__dstack__DOT__depth;
if (dut->rootp->v__DOT___j1__DOT__rstack__DOT__depth > v->rdepth[pc])
v->rdepth[pc] = dut->rootp->v__DOT___j1__DOT__rstack__DOT__depth;
}

PyObject *v3_read(PyObject *_, PyObject *args)
Expand Down
3 changes: 2 additions & 1 deletion j1b/verilator/sim_main.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
#include <stdio.h>
#include "Vj1b.h"
#include "Vj1b___024root.h"
#include "verilated_vcd_c.h"

int main(int argc, char **argv)
Expand All @@ -20,7 +21,7 @@ int main(int argc, char **argv)
fprintf(stderr, "invalid hex value at line %d\n", i + 1);
exit(1);
}
top->v__DOT__ram[i] = v;
top->rootp->v__DOT__ram[i] = v;
}

top->resetq = 0;
Expand Down
3 changes: 2 additions & 1 deletion j1b/verilator/vsim.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
#include <assert.h>
#include "Vj1b.h"
#include "Vj1b___024root.h"
#include "verilated.h"
#define VCD 0
#if VCD
Expand Down Expand Up @@ -59,7 +60,7 @@ Vj1b_init(v3 *self, PyObject *args, PyObject *kwds)
fprintf(stderr, "invalid hex value at line %d\n", i + 1);
exit(1);
}
self->dut->v__DOT__ram[i] = v;
self->dut->rootp->v__DOT__ram[i] = v;
}

return 0;
Expand Down