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Achievement: QuickdrawAchievement: StarstruckAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

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  1. rp32 Public

    RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

    SystemVerilog 11 3

  2. TCB Public

    Tightly Coupled Bus, low complexity, high performance system bus.

    SystemVerilog 1

  3. fri-magisterij Public

    Forked from mitar/fri-latex-templates

    LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.

    PostScript

  4. preimages-2D Public

    2D cellular automata preimages count&list algorithm

    C 3

  5. sockit_cdc Public

    clock domain crossing FIFO

    Verilog 6 2

  6. sockit_owm Public

    SocKit 1-wire (onewire) master

    C 19 6

291 contributions in the last year

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Contribution activity

March 2025

Created 16 commits in 2 repositories

Created a pull request in riscv-software-src/riscof that received 2 comments

update to sail simulator build instructions and plugin, necessary for newer version of sail

The instructions for building sail did not work properly. I updated the instructions and the names of the executables created by the newer version …

+11 −16 lines changed • 2 comments
Opened 1 other pull request in 1 repository
riscv-software-src/riscof 1 closed

Created an issue in verilator/verilator that received 4 comments

Error during build

Git master version of Verilator compiling on Ubuntu 24.04. I will just mention I sometimes experienced errors while compiling with -j8 I usually ju…

4 comments
Opened 2 other issues in 1 repository
SystemRDL/systemrdl-compiler 2 closed
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