Add vilvl/vilvh

README.md

@@ -146,10 +146,6 @@ Vector Multiplication High
 
 ### vpackod.b/h/w/d
 
-### vilvl.b/h/w/d
-
-### vilvh.b/h/w/d
-
 ### vpickev.b/h/w/d
 
 ### vpickod.b/h/w/d

code/gen_impl.py

@@ -219,6 +219,20 @@
             file=f,
         )
         print(f"}}", file=f)
+    with open(f"vilvh_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = (i % 2 == 1) ? a.{m}[i / 2 + {64 // w}] : b.{m}[i / 2 + {64 // w}];",
+            file=f,
+        )
+        print(f"}}", file=f)
+    with open(f"vilvl_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = (i % 2 == 1) ? a.{m}[i / 2] : b.{m}[i / 2];",
+            file=f,
+        )
+        print(f"}}", file=f)
 
 for width in ["s", "d"]:
     m = members_fp[width]

code/gen_tb.py

@@ -39,6 +39,8 @@
     "vextrins": (widths_signed, "v128 a, v128 b, int imm", [0, 3, 7, 15, 16, 32, 64, 128, 255]),
     "vhaddw": (widths_vexth, "v128 a, v128 b"),
     "vhsubw": (widths_vexth, "v128 a, v128 b"),
+    "vilvh": (widths_signed, "v128 a, v128 b"),
+    "vilvl": (widths_signed, "v128 a, v128 b"),
 }
 
 for name in tb:

code/vilvh_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvh_b(v128 a, v128 b) {
+  v128 dst;
+#include "vilvh_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvh_b); }

code/vilvh_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (i % 2 == 1) ? a.byte[i / 2 + 8] : b.byte[i / 2 + 8];
+}

code/vilvh_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvh_d(v128 a, v128 b) {
+  v128 dst;
+#include "vilvh_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvh_d); }

code/vilvh_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (i % 2 == 1) ? a.dword[i / 2 + 1] : b.dword[i / 2 + 1];
+}

code/vilvh_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvh_h(v128 a, v128 b) {
+  v128 dst;
+#include "vilvh_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvh_h); }

code/vilvh_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (i % 2 == 1) ? a.half[i / 2 + 4] : b.half[i / 2 + 4];
+}

code/vilvh_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvh_w(v128 a, v128 b) {
+  v128 dst;
+#include "vilvh_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvh_w); }

code/vilvh_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (i % 2 == 1) ? a.word[i / 2 + 2] : b.word[i / 2 + 2];
+}

code/vilvl_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvl_b(v128 a, v128 b) {
+  v128 dst;
+#include "vilvl_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvl_b); }

code/vilvl_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (i % 2 == 1) ? a.byte[i / 2] : b.byte[i / 2];
+}

code/vilvl_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvl_d(v128 a, v128 b) {
+  v128 dst;
+#include "vilvl_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvl_d); }

code/vilvl_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (i % 2 == 1) ? a.dword[i / 2] : b.dword[i / 2];
+}

code/vilvl_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvl_h(v128 a, v128 b) {
+  v128 dst;
+#include "vilvl_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvl_h); }

code/vilvl_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (i % 2 == 1) ? a.half[i / 2] : b.half[i / 2];
+}

code/vilvl_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vilvl_w(v128 a, v128 b) {
+  v128 dst;
+#include "vilvl_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vilvl_w); }

code/vilvl_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (i % 2 == 1) ? a.word[i / 2] : b.word[i / 2];
+}

docs/lsx/interleave.md

@@ -0,0 +1,11 @@
+# Interleaving
+
+{{ vilvh('b') }}
+{{ vilvh('h') }}
+{{ vilvh('w') }}
+{{ vilvh('d') }}
+
+{{ vilvl('b') }}
+{{ vilvl('h') }}
+{{ vilvl('w') }}
+{{ vilvl('d') }}

main.py

@@ -365,6 +365,24 @@ def vhsubw(name, name2):
             desc=f"Subtract odd-positioned {signedness} {width2}-bit elements in `a` by even-positioned {signedness} {width2}-bit elements in 'b' to get {width}-bit result.",
         )
 
+    @env.macro
+    def vilvh(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vilvh_{name} (__m128i a, __m128i b)",
+            instr=f"vilvh.{name} vr, vr, vr",
+            desc=f"Interleave {width}-bit elements in higher half of `a` and `b`.",
+        )
+
+    @env.macro
+    def vilvl(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vilvl_{name} (__m128i a, __m128i b)",
+            instr=f"vilvl.{name} vr, vr, vr",
+            desc=f"Interleave {width}-bit elements in lower half of `a` and `b`.",
+        )
+
     @env.macro
     def vshuf_hwd(name):
         width = widths[name]