Add vslli/vsrli/vsrai

README.md

@@ -140,12 +140,6 @@ TODO List:
 
 ### vsat.b/h/w/d/bu/hu/wu/du
 
-### vslli.b/h/w/d
-
-### vsrli.b/h/w/d
-
-### vsrai.b/h/w/d
-
 ### vsrlni.b.h/h.w/w.d/d.q
 
 ### vsrlrni.b.h/h.w/w.d/d.q

code/gen_impl.py

@@ -380,20 +380,41 @@
             file=f,
         )
         print(f"}}", file=f)
+    with open(f"vslli_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = a.{m}[i] << imm;",
+            file=f,
+        )
+        print(f"}}", file=f)
     with open(f"vsrl_{width}.h", "w") as f:
         print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
         print(
             f"  dst.{m}[i] = a.{m}[i] >> (b.{m}[i] & 0x{w-1:x});",
             file=f,
         )
         print(f"}}", file=f)
+    with open(f"vsrli_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = a.{m}[i] >> imm;",
+            file=f,
+        )
+        print(f"}}", file=f)
     with open(f"vsra_{width}.h", "w") as f:
         print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
         print(
             f"  dst.{m}[i] = ((s{w})a.{m}[i]) >> (b.{m}[i] & 0x{w-1:x});",
             file=f,
         )
         print(f"}}", file=f)
+    with open(f"vsrai_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = ((s{w})a.{m}[i]) >> imm;",
+            file=f,
+        )
+        print(f"}}", file=f)
     with open(f"vrotr_{width}.h", "w") as f:
         print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
         print(

code/gen_tb.py

@@ -98,14 +98,17 @@
     "vsub": (widths_signed, "v128 a, v128 b"),
     "vsubi": (widths_unsigned, "v128 a, int imm", [0, 31]),
     "vsll": (widths_signed, "v128 a, v128 b"),
+    "vslli": (widths_signed, "v128 a, int imm", [0, 7]),
     "vslt": (widths_all, "v128 a, v128 b"),
     "vslti": (widths_all, "v128 a, int imm", [0, 15]),
     "vsle": (widths_all, "v128 a, v128 b"),
     "vslei": (widths_all, "v128 a, int imm", [0, 15]),
     "vsrl": (widths_signed, "v128 a, v128 b"),
+    "vsrli": (widths_signed, "v128 a, int imm", [0, 7]),
     "vsrlr": (widths_signed, "v128 a, v128 b"),
     "vsrlri": (widths_signed, "v128 a, int imm", [0, 7]),
     "vsra": (widths_signed, "v128 a, v128 b"),
+    "vsrai": (widths_signed, "v128 a, int imm", [0, 7]),
     "vsrar": (widths_signed, "v128 a, v128 b"),
     "vsrari": (widths_signed, "v128 a, int imm", [0, 7]),
     "vsub": (widths_signed, "v128 a, v128 b"),

code/vslli_b.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vslli_b(v128 a, int imm) {
+  v128 dst;
+#include "vslli_b.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vslli_b, 0);
+  FUZZ1(vslli_b, 7);
+}

code/vslli_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = a.byte[i] << imm;
+}

code/vslli_d.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vslli_d(v128 a, int imm) {
+  v128 dst;
+#include "vslli_d.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vslli_d, 0);
+  FUZZ1(vslli_d, 7);
+}

code/vslli_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = a.dword[i] << imm;
+}

code/vslli_h.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vslli_h(v128 a, int imm) {
+  v128 dst;
+#include "vslli_h.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vslli_h, 0);
+  FUZZ1(vslli_h, 7);
+}

code/vslli_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = a.half[i] << imm;
+}

code/vslli_w.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vslli_w(v128 a, int imm) {
+  v128 dst;
+#include "vslli_w.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vslli_w, 0);
+  FUZZ1(vslli_w, 7);
+}

code/vslli_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = a.word[i] << imm;
+}

code/vsrai_b.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrai_b(v128 a, int imm) {
+  v128 dst;
+#include "vsrai_b.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrai_b, 0);
+  FUZZ1(vsrai_b, 7);
+}

code/vsrai_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = ((s8)a.byte[i]) >> imm;
+}

code/vsrai_d.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrai_d(v128 a, int imm) {
+  v128 dst;
+#include "vsrai_d.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrai_d, 0);
+  FUZZ1(vsrai_d, 7);
+}

code/vsrai_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = ((s64)a.dword[i]) >> imm;
+}

code/vsrai_h.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrai_h(v128 a, int imm) {
+  v128 dst;
+#include "vsrai_h.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrai_h, 0);
+  FUZZ1(vsrai_h, 7);
+}

code/vsrai_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = ((s16)a.half[i]) >> imm;
+}

code/vsrai_w.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrai_w(v128 a, int imm) {
+  v128 dst;
+#include "vsrai_w.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrai_w, 0);
+  FUZZ1(vsrai_w, 7);
+}

code/vsrai_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = ((s32)a.word[i]) >> imm;
+}

code/vsrli_b.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrli_b(v128 a, int imm) {
+  v128 dst;
+#include "vsrli_b.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrli_b, 0);
+  FUZZ1(vsrli_b, 7);
+}

code/vsrli_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = a.byte[i] >> imm;
+}

code/vsrli_d.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrli_d(v128 a, int imm) {
+  v128 dst;
+#include "vsrli_d.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrli_d, 0);
+  FUZZ1(vsrli_d, 7);
+}

code/vsrli_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = a.dword[i] >> imm;
+}

code/vsrli_h.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrli_h(v128 a, int imm) {
+  v128 dst;
+#include "vsrli_h.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrli_h, 0);
+  FUZZ1(vsrli_h, 7);
+}

code/vsrli_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = a.half[i] >> imm;
+}

code/vsrli_w.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsrli_w(v128 a, int imm) {
+  v128 dst;
+#include "vsrli_w.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsrli_w, 0);
+  FUZZ1(vsrli_w, 7);
+}

code/vsrli_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = a.word[i] >> imm;
+}

docs/lsx/shift.md

@@ -47,11 +47,21 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vsll('w') }}
 {{ vsll('d') }}
 
+{{ vslli('b') }}
+{{ vslli('h') }}
+{{ vslli('w') }}
+{{ vslli('d') }}
+
 {{ vsrl('b') }}
 {{ vsrl('h') }}
 {{ vsrl('w') }}
 {{ vsrl('d') }}
 
+{{ vsrli('b') }}
+{{ vsrli('h') }}
+{{ vsrli('w') }}
+{{ vsrli('d') }}
+
 {{ vsrlr('b') }}
 {{ vsrlr('h') }}
 {{ vsrlr('w') }}
@@ -67,6 +77,11 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vsra('w') }}
 {{ vsra('d') }}
 
+{{ vsrai('b') }}
+{{ vsrai('h') }}
+{{ vsrai('w') }}
+{{ vsrai('d') }}
+
 {{ vsrar('b') }}
 {{ vsrar('h') }}
 {{ vsrar('w') }}
@@ -85,4 +100,4 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vrotri('b') }}
 {{ vrotri('h') }}
 {{ vrotri('w') }}
-{{ vrotri('d') }}
+{{ vrotri('d') }}

main.py

@@ -695,6 +695,16 @@ def vsll(name):
             desc=f"Logical left shift the unsigned {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
         )
 
+    @env.macro
+    def vslli(name):
+        width = widths[name]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vslli_{name} (__m128i a, imm0_{width-1} imm)",
+            instr=f"vslli.{name} vr, vr, imm",
+            desc=f"Logical left shift the unsigned {width}-bit elements in `a` by `imm`, store the result to `dst`.",
+        )
+
     @env.macro
     def vsrl(name):
         width = widths[name]
@@ -705,6 +715,16 @@ def vsrl(name):
             desc=f"Logical right shift the unsigned {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
         )
 
+    @env.macro
+    def vsrli(name):
+        width = widths[name]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrli_{name} (__m128i a, imm0_{width-1} imm)",
+            instr=f"vsrli.{name} vr, vr, imm",
+            desc=f"Logical right shift the unsigned {width}-bit elements in `a` by `imm`, store the result to `dst`.",
+        )
+
     @env.macro
     def vsra(name):
         width = widths[name]
@@ -715,6 +735,16 @@ def vsra(name):
             desc=f"Arithmetic right shift the signed {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
         )
 
+    @env.macro
+    def vsrai(name):
+        width = widths[name]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrai_{name} (__m128i a, imm0_{width-1} imm)",
+            instr=f"vsrai.{name} vr, vr, imm",
+            desc=f"Arithmetic right shift the signed {width}-bit elements in `a` by `imm`, store the result to `dst`.",
+        )
+
     @env.macro
     def vrotr(name):
         width = widths[name]