Add vmskltz

README.md

@@ -60,8 +60,6 @@ TODO List:
 
 ### vfrstpi.b/h
 
-### vmskltz.b/h/w/d
-
 ### vmskgez.b
 
 ### vmsknz.b

code/gen_tb.py

@@ -72,6 +72,7 @@
     "vmini": (widths_all, "v128 a, int imm", [0, 3, 15]),
     "vmod": (widths_all, "v128 a, v128 b"),
     "vmsub": (widths_signed, "v128 a, v128 b, v128 c"),
+    "vmskltz": (widths_signed, "v128 a"),
     "vmuh": (widths_all, "v128 a, v128 b"),
     "vmul": (widths_signed, "v128 a, v128 b"),
     "vmulwev": (widths_vaddw, "v128 a, v128 b"),

code/vmskltz_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmskltz_b(v128 a) {
+  v128 dst;
+#include "vmskltz_b.h"
+  return dst;
+}
+
+void test() { FUZZ1(vmskltz_b); }

code/vmskltz_b.h

@@ -0,0 +1,14 @@
+u64 m = 0x8080808080808080;
+u64 c = m & a.dword[0];
+c |= c << 7;
+c |= c << 14;
+c |= c << 28;
+c >>= 56;
+dst.dword[0] = c;
+c = m & a.dword[1];
+c |= c << 7;
+c |= c << 14;
+c |= c << 28;
+c >>= 56;
+dst.dword[0] |= c << 8;
+dst.dword[1] = 0;

code/vmskltz_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmskltz_d(v128 a) {
+  v128 dst;
+#include "vmskltz_d.h"
+  return dst;
+}
+
+void test() { FUZZ1(vmskltz_d); }

code/vmskltz_d.h

@@ -0,0 +1,8 @@
+u64 m = 0x8000000000000000;
+u64 c = m & a.dword[0];
+c >>= 63;
+dst.dword[0] = c;
+c = m & a.dword[1];
+c >>= 63;
+dst.dword[0] |= c << 1;
+dst.dword[1] = 0;

code/vmskltz_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmskltz_h(v128 a) {
+  v128 dst;
+#include "vmskltz_h.h"
+  return dst;
+}
+
+void test() { FUZZ1(vmskltz_h); }

code/vmskltz_h.h

@@ -0,0 +1,12 @@
+u64 m = 0x8000800080008000;
+u64 c = m & a.dword[0];
+c |= c << 15;
+c |= c << 30;
+c >>= 60;
+dst.dword[0] = c;
+c = m & a.dword[1];
+c |= c << 15;
+c |= c << 30;
+c >>= 60;
+dst.dword[0] |= c << 4;
+dst.dword[1] = 0;

code/vmskltz_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmskltz_w(v128 a) {
+  v128 dst;
+#include "vmskltz_w.h"
+  return dst;
+}
+
+void test() { FUZZ1(vmskltz_w); }

code/vmskltz_w.h

@@ -0,0 +1,10 @@
+u64 m = 0x8000000080000000;
+u64 c = m & a.dword[0];
+c |= c << 31;
+c >>= 62;
+dst.dword[0] = c;
+c = m & a.dword[1];
+c |= c << 31;
+c >>= 62;
+dst.dword[0] |= c << 2;
+dst.dword[1] = 0;

docs/lsx/misc.md

@@ -15,6 +15,11 @@
 {{ vinsgr2vr('w') }}
 {{ vinsgr2vr('d') }}
 
+{{ vmskltz('b') }}
+{{ vmskltz('h') }}
+{{ vmskltz('w') }}
+{{ vmskltz('d') }}
+
 {{ vpackev('b') }}
 {{ vpackev('h') }}
 {{ vpackev('w') }}

main.py

@@ -816,4 +816,13 @@ def vneg(name):
             intrinsic=f"__m128i __lsx_vneg_{name} (__m128i a)",
             instr=f"vneg.{name} vr, vr",
             desc=f"Negate {width}-bit elements in `a` and save the result in `dst`.",
+        )
+
+    @env.macro
+    def vmskltz(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vmskltz_{name} (__m128i a)",
+            instr=f"vmskltz.{name} vr, vr",
+            desc=f"For each {width}-bit element in `a`, if the element is less than zero, set one bit in `dst`, otherwise clear it.",
         )